MAX11040K_1111 Datasheet, PDF (14/35 Pages) Maxim Integrated Products – 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs

24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Modulator Clock
The modulator clock is created by dividing the frequen-
cy at the XIN input by a factor of 8. The XIN input is dri-
ven either directly by an external clock or by the
on-chip crystal oscillator.
Crystal Oscillator
The on-chip oscillator requires an external crystal (or
resonator) with a 24.576MHz operating frequency con-
nected between XIN and XOUT, as shown in Figure 3.
As in any crystal-based oscillator circuit, the oscillator
frequency is sensitive to the capacitive load (C_L). C_L is
the capacitance that the crystal needs from the oscilla-
tor circuit and not the capacitance of the crystal. The
input capacitance across XIN and XOUT is 1.5pF.
Choose a crystal with a 24.576MHz oscillation frequen-
cy and an ESR less than 30Ω, such as the MP35 from
RXD Technologies. See Figure 3 for the block diagram
of the crystal oscillator. Set XTALEN = 1 in the configu-
ration register to enable the crystal oscillator. The
CLKOUT output provides a buffered version of the
clock that is capable of driving eight devices, allowing
synchronized operation from a single crystal. See the
Multiple Device Synchronization section in the
Applications Information section.
External Clock
To use an external clock, set XTALEN = 0 in the
Configuration register and connect an external clock
source (20MHz–25MHz) to XIN. CLKOUT becomes
high impedance.
20pF
XIN
24.576MHz
XOUT
20pF
MAX11040K
MAX11060
24.576MHz
OSCILLATOR
Figure 3. Crystal Oscillator Input
Analog Input Overvoltage
and Fault Protection
The full-scale differential input range of the devices is
±0.88V_REF. The converter accurately represents any
input for which the positive and negative analog inputs
are separated by a magnitude of less than 0.88V_REF.
The device includes special circuitry that protects it
against voltages on the analog inputs up to +6V.
Setting FAULTDIS = 1 disables the protection circuitry.
There are two mechanisms of overvoltage detection
and protection: full-scale overflow and overvoltage
fault. Full-scale overflow occurs if the magnitude of the
applied input voltage on any one or more channels is
greater than 0.88V_REF. In this case, the digital output is
clipped to positive or negative full scale and the OVRFLW
flag goes low. Overvoltage fault occurs if the magni-
tude of an applied input voltage on any one or more
channels goes outside the fault-detection thresholds.
The reaction to an overvoltage fault is dependent on
whether the fault-protection circuitry is enabled. If
enabled, the input-protection circuits engage and the
FAULT flag goes low. A full-scale overflow or an over-
voltage fault condition on any one channel does not
affect the output data for the other channels.
The input protection circuits allow up to ±6V relative to
AGND on each input, and up to ±6V differentially
between AIN+ and AIN-, without damaging the devices
only if the following conditions are satisfied: power is
applied, the devices are not in shutdown mode, a clock
frequency of at least 20MHz is available at XIN, and
FAULTDIS = 0. The analog inputs allow up to ±3.5V rel-
ative to AGND when either devices are placed in shut-
down mode, the clock stops, or FAULTDIS = 1.
During an overvoltage fault condition, the impedance
between AIN_+ and AIN_- reduces to as low as 0.5kΩ.
The output structure and cascading features of FAULT
and OVRFLW are discussed in the Multiple Device
Digital Interface section.
Analog Input Overflow
Detection and Recovery (OVRFLW)
The OVRFLW flag is set based on the ADC conversion
result. When the applied voltage on one or more analog
inputs goes outside the positive or negative full scale
(±0.88V_REF), OVRFLW asserts after a delay defined by
the latency of the converter, coincident with the DRDYOUT
of the full-scale clamped conversion result (see Figure
4). The specifics of the latency are discussed earlier in
the data sheet in the Latency section.
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