MAX16067 Datasheet, PDF (40/47 Pages) Maxim Integrated Products – 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
BYPASS: When the BYPASS instruction is latched into
the instruction register, TDI connects to TDO through the
1-bit bypass test data register. This allows data to pass
from TDI to TDO without affecting the device’s operation.
IDCODE: When the IDCODE instruction is latched into
the parallel instruction register, the identification data
register is selected. The device identification code is
loaded into the identification data register on the rising
edge of TCK following entry into the capture-DR state.
Shift-DR can be used to shift the identification code
out serially through TDO. During test-logic-reset, the
IDCODE instruction is forced into the instruction register.
The identification code always has a ‘1’ in the LSB posi-
tion. The next 11 bits identify the manufacturer’s JEDEC
number and number of continuation bytes followed by
16 bits for the device and 4 bits for the version. See
Table 29.
USERCODE: When the USERCODE instruction latches
into the parallel instruction register, the user-code data
register is selected. The device user-code loads into the
user-code data register on the rising edge of TCK fol-
lowing entry into the capture-DR state. Shift-DR can be
used to shift the user-code out serially through TDO. See
Table 30. This instruction can be used to help identify
multiple MAX16067 devices connected in a JTAG chain.
LOAD ADDRESS: This is an extension to the standard
IEEE 1149.1 instruction set to support access to the
memory in the MAX16067. When the LOAD ADDRESS
instruction latches into the instruction register, TDI con-
nects to TDO through the 8-bit memory address test
data register during the shift-DR state.
READ DATA: This is an extension to the standard
IEEE 1149.1 instruction set to support access to the
memory in the MAX16067. When the READ instruction
latches into the instruction register, TDI connects to TDO
through the 8-bit memory read test data register during
the shift-DR state.
WRITE DATA: This is an extension to the standard
IEEE 1149.1 instruction set to support access to the
memory in the MAX16067. When the WRITE instruction
latches into the instruction register, TDI connects to TDO
through the 8-bit memory write test data register during
the shift-DR state.
REBOOT: This is an extension to the standard IEEE
1149.1 instruction set to initiate a software controlled
reset to the MAX16067. When the REBOOT instruc-
tion latches into the instruction register, the MAX16067
resets and immediately begins the boot-up sequence.
SAVE: This is an extension to the standard IEEE 1149.1
instruction set that triggers a fault log. The current ADC
conversion results along with fault information are saved
to flash depending on the configuration of the Critical
Fault Log Control register (r6Dh).
Table 29. 32-Bit Identification Code
MSB
VERSION (4 BITS) PART NUMBER (16 BITS)
0001
1000000000000001
MANUFACTURER (11 BITS)
00011001011
LSB
FIXED VALUE (1 BIT)
1
Table 30. 32-Bit User-Code Data
MSB
DON’T CARE
00000000000000000
SMBUS SLAVE ID
See Table 26
LSB
USER ID (r8A[7:0])
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