MAX16067 Datasheet, PDF(28/47 Page) Maxim Integrated Products – 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

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6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

the watchdog timer expires. RESET is not affected by

the watchdog timer when the Watchdog Reset Output

Enable bit (r76h[7]) is set to â0â. If a RESET is asserted

by the watchdog timeout, the WDRESET bit is set to â1â. A

connected processor can check this bit to see the reset

was due to a watchdog timeout.

See Table 23 for more information on configuring watch-

dog functionality.

Independent Watchdog Timer Operation

When r73h[3] is â1,â the watchdog timer operates in

the independent mode. In the independent mode, the

watchdog timer operates as if it were a separate device.

The watchdog timer is activated immediately upon VCC

exceeding UVLO and once the boot-up sequence is fin-

ished. When RESET is asserted by the sequencer state

machine, the watchdog timer and WDO are not affected.

There is a startup delay if r76h[6:4] is set to a value dif-

ferent than â000â. If r76h[6:4] is set to â000â, there is not a

startup delay. See Table 23 for delay times.

In independent mode, if the Watchdog Reset Output

Enable bit r76h[7] is set to â1,â when the watchdog timer

expires, WDO asserts then RESET asserts. WDO is then

deasserts. WDO is low for approximately 1Fs. If the

Watchdog Reset Output Enable bit (r76h[7]) is set to

â0,â when the watchdog timer expires, WDO asserts but

RESET is not affected.

LAST MON_

WDI

VTH

tWDI_STARTUP

tRP

RESET

Figure 6. Normal Watchdog Startup Sequence

VCC

WDI

< tWDI

tWDI

VCC

WDO

Figure 7. Watchdog Timer Operation

> tWDI

< tWDI

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