MAX16067 Datasheet, PDF (27/47 Pages) Maxim Integrated Products – 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
Table 22. Reset Output Configuration (continued)
REGISTER
ADDRESS
3Ch
3Dh
FLASH
ADDRESS
23Ch
23Dh
BIT RANGE
DESCRIPTION
[0]
[1]
[2]
[3]
[4]
[5]
[7:6]
[0]
[1]
[2]
[3]
[4]
[5]
[7:6]
1 = RESET depends on MON1 undervoltage
1 = RESET depends on MON2 undervoltage
1 = RESET depends on MON3 undervoltage
1 = RESET depends on MON4 undervoltage
1 = RESET depends on MON5 undervoltage
1 = RESET depends on MON6 undervoltage
Not used
1 = RESET depends on MON1 overvoltage
1 = RESET depends on MON2 overvoltage
1 = RESET depends on MON3 overvoltage
1 = RESET depends on MON4 overvoltage
1 = RESET depends on MON5 overvoltage
1 = RESET depends on MON6 overvoltage
Not used
Watchdog Timer
The watchdog timer operates together with or indepen-
dently of the MAX16067. When operating in dependent
mode, the watchdog is not activated until the sequenc-
ing is complete and RESET is deasserted. When oper-
ating in independent mode, the watchdog timer is
independent of the sequencing operation and activates
immediately after VCC exceeds the UVLO threshold
and the boot phase is complete. Set r73h[4] to ‘0’ to
configure the watchdog in dependent mode. Set r73h[4]
to ‘1’ to configure the watchdog in independent mode.
See Table 23 for more information on configuring the
watchdog timer in dependent or independent mode. The
watchdog timer can be reset by toggling the WDI input
(GPIO4) or by writing a ‘1’ to r75h[5].
Dependent Watchdog Timer Operation
Use the watchdog timer to monitor FP activity in two
modes. Flexible timeout architecture provides an adjust-
able watchdog startup delay of up to 300s, allowing
complicated systems to complete lengthy boot-up rou-
tines. An adjustable watchdog timeout allows the super-
visor to provide quick alerts when the processor activity
fails. After each reset event (VCC drops below UVLO
then returns above UVLO, software reboot, manual reset
(MR), EN input going low then high, or watchdog reset)
and once sequencing is complete, the watchdog startup
delay provides an extended time for the system to power
up and fully initialize all FP and system components
before assuming responsibility for routine watchdog
updates. Set r76h[6:4] to a value other than ‘000’ to
enable the watchdog startup delay. Set r76h[6:4] to ‘000’
to disable the watchdog startup delay.
The normal watchdog timeout period, tWDI, begins after
the first transition on WDI before the conclusion of the
long startup watchdog period, tWDI_STARTUP (Figures 6
and 7). During the normal operating mode, WDO asserts
if the FP does not toggle WDI with a valid transition (high-
to-low or low-to-high) within the standard timeout period,
tWDI. WDO remains asserted until WDI is toggled or
RESET is asserted (Figure 7).
While EN is low, the watchdog timer is in reset. The
watchdog timer does not begin counting until the power-
on mode is reached and RESET is deasserted. The
watchdog timer is reset and WDO deasserts any time
RESET is asserted (Figure 8). The watchdog timer is
held in reset while RESET is asserted.
The watchdog can be configured to control the RESET
output as well as the WDO output. RESET asserts for
the reset timeout, tRP, when the watchdog timer expires
and the Watchdog Reset Output Enable bit (r76h[7]) is
set to ‘1’. When RESET is asserted, the watchdog timer
is cleared and WDO is deasserted, therefore, WDO
pulses low for a short time (approximately 1Fs) when
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