MAX16067 Datasheet, PDF (11/47 Pages) Maxim Integrated Products – 6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
Table 1. Current Sequencer Slot
REGISTER
ADDRESS
BIT RANGE
Current-sequencer state
0000 = Slot0
0001 = Slot1
0010 = Slot2
0011 = Slot3
[3:0]
0100 = Slot4
21h
0101 = Slot5
0110 = Slot6
0111 = Power-on mode
1000 = Fault state
1001 to 1111 = Unused
[7:4]
Reserved
DESCRIPTION
A sequencing delay occurs between each slot and is
configured in registers 77h–7Dh as shown in Table 2.
Each sequencing delay is stored as an 8-bit value and
is calculated as follows:
( ) ^tSEQ ^{= 5 ×10 −6 × 2a × (16 + b)}
where tSEQ is in seconds, a is the decimal value of the
4 MSBs and b is the decimal value of the 4 LSBs. See
Table 3 for example calculations.
Enable Input (EN)
To initiate sequencing and enable monitoring, the volt-
age at EN must be above 1.24V (typ) and the software
enable bit in r73h[0] must be set to ‘1.’ To power down
and disable monitoring, either pull EN below 1.215V
(typ) or set the software enable bit to ‘0.’ See Table 4 for
the software enable bit configurations. Connect EN to
ABP if not used.
If a fault condition occurs during the power-up cycle,
the EN_OUT_ outputs are powered down immediately,
regardless of the state of EN. In the monitoring state,
if EN falls below the threshold, the sequencing state
machine begins the power-down sequence. If EN rises
above the threshold during the power-down sequence,
the sequence state machine continues the power-down
sequence until all the channels are powered off and then
the device immediately begins the power-up sequence.
When in the monitoring state, and when EN falls below
the undervoltage threshold, a register bit, ENRESET
(r20h[2]), is set to a ‘1.’ This register bit latches and must
be cleared through software. This bit indicates if RESET
asserted low due to EN going under the threshold. The
POR state of ENRESET is ‘0’. The bit is only set on a fall-
ing edge of the EN comparator output or the software
enable bit. If operating in latch-on fault mode, toggle
EN or toggle the software enable bit to clear the latch
condition and restart the device once the fault condition
has been removed.
Table 2. Slot Delay Register
REGISTER
ADDRESS
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
FLASH
ADDRESS
277h
278h
279h
27Ah
27Bh
27Ch
27Dh
BIT RANGE
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
DESCRIPTION
Sequence slot 0 to slot 1 delay
Sequence slot 1 to slot 2 delay
Sequence slot 2 to slot 3 delay
Sequence slot 3 to slot 4 delay
Sequence slot 4 to slot 5 delay
Sequence slot 5 to slot 6 delay
Sequence slot 6 to power-on state delay
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