MAX1021 Datasheet, PDF (35/40 Pages) Maxim Integrated Products – 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
DIN
CS
SCLK
(CONVERSION BYTE)
(ACQUISITION1)
(CONVERSION1)
(ACQUISITION2)
DOUT
MSB1
LSB1
MSB2
EOC
X = DON'T CARE.
Figure 9. Clock Mode 11—Externally Timed Acquisition, Sampling, and Conversion Without CNVST
DAC/GPIO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing speci-
fications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DAC-
register update. For a software-command DAC-register
update, t_S is valid from the rising edge of CS, which fol-
lows the last data bit in the software command word.
LDAC Functionality
Drive LDAC low to transfer the content of the input
registers to the DAC registers. Drive LDAC permanently
low to make the DAC register transparent. The DAC
output typically settles from zero to full scale within ±1
LSB after 2µs. See Figure 14.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Ensure that digi-
tal and analog signal lines are separated from each
other. Do not run analog and digital signals parallel to
one another (especially clock signals) or do not run dig-
ital lines underneath the MAX1021/MAX1043
package. High-frequency noise in the AV_DD power
supply may affect performance. Bypass the AV_DD sup-
ply with a 0.1µF capacitor to AGND, close to the AV_DD
pin. Bypass the DV_DD supply with a 0.1µF capacitor to
DGND, close to the DV_DD pin. Minimize capacitor lead
lengths for best supply-noise rejection. If the power
supply is very noisy, connect a 10Ω resistor in series
with the supply to improve power-supply filtering.
The MAX1021/MAX1043 thin QFN packages contain an
exposed pad on the underside of the device. Connect
this exposed pad to AGND. Refer to the MAX1258 EV kit
for an example of proper layout.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1021/MAX1043 is measured using the end-
point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Unipolar ADC Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB, above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal first transition point.
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