MAX1021 Datasheet, PDF (20/40 Pages) Maxim Integrated Products – 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
The LSB is followed by 2 sub-bits. If another tempera-
ture measurement is performed before the first temper-
ature result is read out, the old measurement is
overwritten by the new result. Temperature results are
in degrees Celsius (two’s complement), at a resolution
of 8 LSB per degree. See the Temperature
Measurements section for details on converting the dig-
ital code to a temperature.
10-Bit DAC
In addition to the 10-bit ADC, the MAX1021/MAX1043
also include eight (MAX1021) or four (MAX1043) volt-
age-output, 10-bit, monotonic DACs with less than 1
LSB integral nonlinearity error and less than 0.5 LSB
differential nonlinearity error. Each DAC has a 2µs set-
tling time and ultra-low glitch energy (4nV•s). The 10-bit
DAC code is unipolar binary with 1 LSB = V_REF / 1024.
DAC Digital Interface
Figure 1 shows the MAX1021 functional diagram. The
shift register converts a serial 16-bit word to parallel
data for each input register operating with a clock rate
up to 25MHz. The SPI-compatible digital interface to the
shift register consists of CS, SCLK, DIN, and DOUT.
Serial data at DIN is loaded on the falling edge of SCLK.
Pull CS low to begin a write sequence. Begin a write to
the DAC by writing 0001XXXX as a command byte. The
last 4 bits of the DAC select register are don’t-care bits.
See Table 10. Write another 2 bytes to the DAC inter-
face register following the command byte to select the
appropriate DAC and the data to be written to it. See
Tables 17 and 18.
The double-buffered DACs include an input and a DAC
register. The input registers are directly connected to
the shift register and hold the result of the most recent
write operation. The 10-bit DAC registers hold the cur-
rent output code for the respective DAC. Data can be
transferred from the input registers to the DAC registers
by pulling LDAC low or by writing the appropriate DAC
command sequence at DIN. See Table 17. The outputs
of the DACs are buffered through eight (MAX1021)/ four
(MAX1043) rail-to-rail op amps.
The MAX1021/MAX1043 DAC output voltage range is
based on the internal reference or an external refer-
ence. Write to the setup register (see Table 5) to pro-
gram the reference. If using an external voltage
reference, bypass REF1 with a 0.1µF capacitor to
AGND. The internal reference is 2.5V. When using an
external reference on these devices, the voltage range
is 0.7V to AV_DD.
DAC Transfer Function
See Table 2 for various analog outputs from the DAC.
DAC Power-On Wake-Up Modes
The state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AV_DD or
AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩ internal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AV_DD to wake up all DAC outputs
at 3FFh. While RES_SEL is high, the 100kΩ pullup
resistor pulls the DAC outputs to V_REF1 and the output
buffers are powered down.
DAC Power-Up Modes
See Table 18 for a description of the DAC power-up
and power-down modes.
GPIOs
In addition to the internal ADC and DAC, the
MAX1021/MAX1043 also provide four GPIO channels,
GPIOA0, GPIOA1, GPIOC0, and GPIOC1.
Read and write to the GPIOs as detailed in Tables 1
and 12–16. Also, see the GPIO Command section. See
Figures 11 and 12 for GPIO timing.
Table 2. DAC Output Code Table
DAC CONTENTS
MSB
LSB
11
1111 1111
ANALOG OUTPUT
+V_REF
⎛ ₁₀₂₃ ⎞
⎜⎟
⎝ 1024 ⎠
10
0000 0001
+V_REF
⎛ ₁₀₂₃ ⎞
⎜⎟
⎝ 1024 ⎠
10
0000
0000
+V_REF
⎛ ₅₁₂ ⎞
⎜⎟
⎝ 1024 ⎠
=
⎛ _+VREF ⎞
⎜
⎟
⎝ 2⎠
01
0111 0111
+V_REF
⎛
⎜
511 ^⎞
⎟
⎝ 1024 ⎠
00
0000 0001
00
0000 0000
⎛
+V_{REF ⎜}
1
⎞
⎟
⎝ 1024 ⎠
0
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