MAX1021 Datasheet, PDF (15/40 Pages) Maxim Integrated Products – 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Description
PIN
MAX1021 MAX1043
1, 2
1, 2
3
3
4
4
5
5
NAME
FUNCTION
GPIOA0, GPIOA1 General-Purpose I/O A0, A1. GPIOA0, GPIOA1 can sink and source 15mA.
EOC
Active-Low, End-of-Conversion Output. Data is valid after the falling edge of EOC.
DV_DD
Digital Positive-Power Input. Bypass DV_DD to DGND with a 0.1µF capacitor.
DGND
Digital Ground. Connect DGND to AGND.
Serial-Data Output. Data is clocked out on the falling edge of the SCLK clock in
6
6
DOUT
modes 00, 01, and 10. Data is clocked out on the rising edge of the SCLK clock
in mode 11. It is high impedance when CS is high.
7
7
SCLK
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty cycle must be
40% to 60%). See Table 5 for details on programming the clock mode.
8
8
—
9–12, 16–19
13
14
15, 23, 32, 33
9–12
—
13
14
15, 23, 32, 33
20
20
21
21
DIN
OUT0–OUT3
OUT0–OUT7
AV_DD
AGND
N.C.
LDAC
CS
Serial-Data Input. DIN data is latched into the serial interface on the falling edge
of SCLK.
DAC Outputs
DAC Outputs
Positive Analog Power Input. Bypass AV_DD to AGND with a 0.1µF capacitor.
Analog Ground
No Connection. Not internally connected.
Active-Low, Load DAC. LDAC is an asynchronous active-low input that updates
the DAC outputs. Drive LDAC low to make the DAC registers transparent.
Active-Low, Chip-Select Input. When CS is low, the serial interface is enabled.
When CS is high, DOUT is high impedance.
22
24, 25
26
27–31, 34
35
22
24, 25
26
27–31, 34
35
RES_SEL
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up the DAC
outputs with a 100kΩ resistor to GND or set RES_SEL high to wake up the DAC outputs
with a 100kΩ resistor to V_REF. The default is the external V_REF.
GPIOC0, GPIOC1 General-Purpose I/O C0, C1. GPIOC0, GPIOC1 can sink 4mA and source 2mA.
REF1
Reference 1 Input. Reference voltage; leave unconnected to use the internal
reference (2.5V). REF1 is the positive reference in ADC differential mode. Bypass
REF1 to AGND with a 0.1µF capacitor in external reference mode only. See the
ADC/DAC References section.
AIN0–AIN5 Analog Inputs
REF2/AIN6
Reference 2 Input/Analog Input Channel 6. See Table 5 for details on
programming the setup register.
36
36
CNVST/AIN7 ^{Active-Low, Conversion-Start Input/Analog Input 7. See Table 5 for details on}
programming the setup register.
—
16-19
D.C.
Do Not Connect. Do not connect to this pin.
—
—
EP
Exposed Pad. Must be externally connected to AGND. Do not use as a ground
connect.
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