MAX15022_11 Datasheet, PDF (24/28 Pages) Maxim Integrated Products – Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Dual LDO Controllers

Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
Minimum Load Requirements
(Linear Regulators)
Under no-load conditions, leakage currents from the
pass transistors supply the output capacitor, even
when the transistor is off. Generally, this is not a prob-
lem since the feedback resistors’ current drains the
excess charge. However, charge can build up on the
output capacitor over temperature, making output volt-
age rise above its set point. Care must be taken to
ensure the feedback resistors’ current exceeds the
pass transistor’s leakage current over the entire tem-
perature range.
Thermal Consideration
The power dissipated by the pass transistor is calculat-
ed by:
P_P3/4 = ₍V_IN − ₎ V_OUT3/4 × I_OUT3/4
where V_IN is the input to the transistor of the LDO.
Heatsink the transistor adequately to prevent a thermal
runaway condition. Refer to the transistor data sheet for
thermal calculations.
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve clean and sta-
ble operation. Follow these guidelines for good PCB
layout:
1) Place decoupling capacitors as close as possible to
the IC pins.
2) Keep SGND and PGND isolated. Connect them at
one single point typically close to the negative ter-
minal of the input filter capacitor. Use as short a
trace as possible.
3) Route high-speed switching nodes (LX_) away from
sensitive analog areas (FB_, COMP_, B_, and EN_).
4) Distribute the power components evenly across the
board for proper heat dissipation.
5) Ensure all feedback connections are short and
direct. Place feedback resistors as close as possi-
ble to the IC.
6) Place the output capacitors close to the load.
7) Connect the MAX15022 exposed pad to a large
copper plane to maximize its power dissipation
capability. Thermal resistances can be obtained
using the method described in JEDEC specification
JESD51-7. Connect the exposed pad to SGND
plane. Do not connect the exposed pad to the
SGND pin directly underneath the IC.
8) Use 2oz. copper to keep trace inductance and
resistance to a minimum. Thin copper PCBs can
compromise efficiency since high currents are
involved in the application. Also thicker copper con-
ducts heat more effectively, thereby reducing ther-
mal impedance.
9) A reference PCB layout included in the MAX15022
Evaluation Kit is also provided to further aid layout.
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