MAX15022_11 Datasheet, PDF (21/28 Pages) Maxim Integrated Products – Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Dual LDO Controllers

Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
The locations of the zeros and poles should be such
that the phase margin peaks around f_CO.
Set the ratios of f_CO-to-f_Z and f_P-to-f_CO equal to one anoth-
er, e.g., ^fCO ^{= f}P = 5 is a good number to get approximately
f_Z f_CO
60° of phase margin at f_CO. Whichever technique, it is
important to place the two zeros at or below the double
pole to avoid the conditional stability issue.
The following procedure is recommended:
1) Select a crossover frequency, f_CO, at or below one-
tenth the switching frequency (f_SW):
f_CO [kHz]
≤
f_SW [kHz]
10
2) Calculate the LC double-pole frequency, f_LC :
f_LC[MHz] ≈
1
2π × L[µH] × C_OUT[µF]
where C_OUT is the output capacitor of the regulator.
3) Select the feedback resistor, R_F, in the range of
3.3kΩ to 30kΩ.
4)
Place the compensator’s first zero
at or below the output filter’s dou-
f_Z1
=
1
2π ×R_F
× C_F
ble-pole, f_LC , as follows:
C_F
[µF]
=
2π
×
R_F
[kΩ]
1
× 0.5
×
f_LC [kHz]
5) The gain of the modulator (Gain_MOD)—comprised of
the regulator’s PWM, LC filter, feedback divider, and
associated circuitry—at the crossover frequency is:
Gain_MOD
=
4
×
(2π
×
f_CO [MHz])²
1
× L[µH]×
C_OUT [µF]
The gain of the error amplifier (Gain_E/A) in midband fre-
quencies is:
Gain_E/A = 2π × f_CO[kHz]× C_I[µF]× R_F[kΩ]
The total loop gain is the product of the modulator gain
and the error amplifier gain at f_CO should be equal to 1,
as follows:
Gain_MOD x Gain_E/A = 1
So:
4
×
(2π
×
f_CO[kHz])²
1
× C_OUT[µF]
×
L[µH]
× 2π × f_CO[kHz] × C_I[pF] × R_F[kΩ] = 1
Solving for C_I:
C_I [pF]
=
(^2π
) ^{× f}_CO^{[kHz]× L[µH]× C}_OUT^[µF]
4 × R_F[kΩ]
6) For those situations where f_LC < f_CO < f_ESR < f_SW/2,
as with low-ESR tantalum capacitors, the compen-
sator’s second pole (f_P2) should be used to cancel
f_ESR. This provides additional phase margin. On the
system Bode plot, the loop gain maintains its
+20dB/decade slope up to 1/2 of the switching fre-
quency verses flattening out soon after the 0dB
crossover. Then set:
f_P2 = f_ESR
If a ceramic capacitor is used, then the capacitor ESR
zero, f_ESR, is likely to be located even above 1/2 of the
switching frequency, that is f_LC < f_CO < f_SW/2 < f_ESR. In
this case, the frequency of the second pole (f_P2) should
be placed high enough not to significantly erode the
phase margin at the crossover frequency. For example,
f_P2 can be set at 5 x f_CO, so that its contribution to phase
loss at the crossover frequency f_CO is only about 11°:
f_P2 = 5 x f_CO
Once f_P2 is known, calculate R_I:
R_I [kΩ]
=
2π
×
f_P2
1
[kHz]× C_I[µF]
7) Place the second zero (f_Z2) at 0.2 x f_CO or at f_LC,
whichever is lower, and calculate R₁ using the fol-
lowing equation:
R₁[kΩ]
=
2π
×
1
f_Z2[kHz] ×
C_I[µF]
8) Place the third pole (f_P3) at 1/2 the switching fre-
quency and calculate C_CF from:
C_CF [nF]
=
(^2π
× 0.5
×
f_SW
1
[MHz] ×
R_F
[kΩ]₎
9) Calculate R₂ as:
R₂
[kΩ]
=
R₁[kΩ] ×
V_FB [V]
V_{OUT_} [V] − V_FB
[V]
where V_FB = 0.6V (typ).
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