MAX15022_11 Datasheet, PDF (22/28 Pages) Maxim Integrated Products – Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Dual LDO Controllers

Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
LDO Controllers
Design Procedure
PNP Pass Transistors Selection
The pass transistors must meet specifications for current
gain (ß), input capacitance, collector-emitter saturation
voltage, and power dissipation. The transistor’s current
gain limits the guaranteed maximum output current to:
I_OUT3/4[A]
=
⎛
⎝⎜^{IB3/4(MIN)[A]}
−
R_P^V_UBELL^[V[Ω^] ]^{⎞⎠⎟}
×
β
where I_B3/4(MIN) is the minimum base-drive current and
R_PULL is the pullup resistor connected between the
transistor’s base and emitter.
In addition, to avoid premature dropout, V_CE-SAT must
be less than or equal to (V_{PVIN_(MIN)} - V_OUT3/4).
Furthermore, the transistor’s current gain increases the
linear regulator’s DC loop gain (see the Stability
Requirements section), so excessive gain destabilizes
the output. Therefore, transistors with high current gain
at the maximum output current, such as Darlington
transistors, are not recommended. The transistor’s
input capacitance and input resistance also create a
second pole, which could be low enough to destabilize
the LDO when the output is heavily loaded.
The transistor’s saturation voltage at the maximum out-
put current determines the minimum input-to-output volt-
age differential that the linear regulator supports.
Alternately, the package’s power dissipation could limit
the useable maximum input-to-output voltage differential.
The maximum power-dissipation capability of the tran-
sistor’s package and mounting must support the actual
power dissipation in the device without exceeding the
maximum junction temperature. The power dissipated
equals the maximum load current multiplied by the
maximum input-to-output voltage differential.
Output 3 and Output 4 Voltage Selection
The MAX15022 positive linear-regulator output voltage
is set with a resistive divider from the desired output
(V_OUT3/4) to FB3/4 to SGND (see Figures 7 and 8).
First, select the R_2FB3/4 resistance value (below 30kΩ).
Then, solve for R_1FB3/4:
R_1FB3/4[kΩ]
=
⎛
R_2FB3/4[kΩ]_⎝⎜
V_OUT3/4[V]
V_FB3/4[V]
⎞
− 1_⎠⎟
where V_OUT3/4 can support output voltages as low as
0.6V and V_FB3/4 is 0.6V (typ).
Stability Requirements
The MAX15022’s B3 and B4 outputs are designed to
drive bipolar PNP transistors. These PNP transistors
form linear regulators with positive outputs. An internal
transconductance amplifier drives the external pass
transistors. The transconductance amplifier, pass tran-
sistor’s specifications, the base-emitter resistor, and the
output capacitor determine the loop stability.
The total DC loop gain (A_V) is the product of the gains of
the internal transconductance amplifier, the gain from
base to collector of the pass transistor, and the attenua-
tion of the feedback divider. The transconductance ampli-
fier regulates the output voltage by controlling the pass
transistor’s base current. Its DC gain is approximately:
g_{C_}
×
⎛
⎝⎜
R_IN
R_IN
×
+
R_P1/2
R_P1/2
⎞
⎠⎟
where g_{C_} is the transconductance of the internal
amplifier and is typically 1.2mA/mV, R_P1/2 is the resistor
across the base and the emitter of the pass transistor in
kΩ, and R_IN is the input resistance of the pass transis-
tor, and can be calculated by:
R_IN[kΩ] = β
x
⎛ _26[mV] ⎞
⎝⎜ ^IOUT3/4^[µA]⎠⎟
The DC gain for the pass transistor (A_P), including the
feedback divider, is approximately:
A_P
=
g_m−PNP
× ^{⎡⎢ROUT3/4 × (R1FB3/4}
⎣ ^ROUT3/4 ^{+ R}1FB3/4
+
R_2FB3/4
)^⎤
⎥
+ R_{2FB3/4 ⎦}
×
R_2FB3/4
R_1FB3/4 + R_2FB3/4
where
g_m−PNP
=
I_{OUT3/4 [}mA_]
26 _[mV_]
.
The total DC loop gain for output 3 and output 4 is:
A_V
=
g_{C_}
×
⎛
⎝⎜
R_IN
R_IN
× R_P1/2
+ R_P1/2
⎞
⎠⎟
×
A_P
The output capacitance (C_{OUT_}) and the load resis-
tance (R_{OUT_}) create a dominant pole (f_POLE1) at:
f_POLE1[kHz]
=
2π
×
1
C_OUT3/4[µF]
× R_OUT3/4[kΩ]
=
I_OUT3/4(MAX)[mA]
2π × C_OUT3/4[µF] × V_OUT3/4[V]
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