MAX15022_11 Datasheet, PDF (19/28 Pages) Maxim Integrated Products – Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Dual LDO Controllers

Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
Type II: Compensation when f_CO > f_{ZERO, ESR}
When the f_CO is greater than f_ESR, a Type II compensa-
tion network provides the necessary closed-loop com-
pensated response. The Type II compensation network
provides a midband compensating zero and a high-fre-
quency pole (see Figures 5a and 5b).
R_FC_F provides the midband zero f_MID,ZERO, and
R_FC_CF provides the high-frequency pole, f_HIGH,POLE.
Use the following procedure to calculate the compen-
sation network components.
Calculate the f_ESR and LC double pole, f_LC:
f_ESR
=
1
2π × ESR × C_OUT
f_LC ≈
1
2π × L × C_OUT
where C_OUT is the regulator output capacitor and ESR
is the series resistance of C_OUT. See the Output-
Capacitor Selection section for more information on cal-
culating C_OUT and ESR.
Set the compensator’s leading zero, f_Z1, at or below the
filter’s resonant double-pole frequency from:
f_Z1 ≤ f_LC
Set the compensator’s high-frequency pole, f_P1, at or
below one-half the switching frequency, f_SW:
f_P1
≤
f_SW
2
To maximize the compensator’s phase lead, set the
desired crossover frequency, f_CO, equal to the geomet-
ric mean of the compensator’s leading zero, f_Z1, and
high-frequency pole, f_P1, as follows:
f_CO = f_Z1 × f_P1
Select the feedback resistor, R_F, in the range of 3.3kΩ
to 30kΩ.
Calculate the gain of the modulator (Gain_MOD)—com-
prised of the regulator’s PWM, LC filter, feedback divider,
and associated circuitry—at the desired crossover fre-
quency, f_CO, using the following equation:
( ) ^{GainMOD = 4(V/V)×}
ESR [mΩ]
2π × f_CO[kHz] × L[µH]
× ^{VFB [V]}
V_{OUT_} [V]
where V_FB is the 0.6V (typ) FB_ input-voltage set-point,
L is the value of the regulator inductor, ESR is the
V_{OUT_}
R1
C_CF
R_F
C_F
FB_
R2
VREF
Figure 5a. Type II Compensation Network
GAIN
(dB)
COMP_
1ST ASYMPTOTE
(ωR₁C_F)^-1
2ND ASYMPTOTE
( )RF -1
R_I
3RD ASYMPTOTE
(ωR_FC_CF)^-1
1ST POLE
(AT ORIGIN)
1ST ZERO
(R_FC_F)^-1
2ND POLE
(R_FC_CF)^-1
ω (rad/sec)
Figure 5b. Type II Compensation Network Response
series resistance of the output capacitor, and V_{OUT_} is
the desired output voltage.
The gain of the error amplifier (Gain_E/A) in the midband
frequencies is:
Gain_E/A
=
R_F
R₁
[kΩ]
[kΩ]
The total loop gain is the product of the modulator gain
and the error amplifier gain at f_CO and should be set
equal to 1 as follows:
Gain_MOD x Gain_E/A = 1
So:
20
×
log₁₀
⎡
⎢
⎣
R_F
R₁
⎤
⎥
⎦
+
20
×
log₁₀
⎡
⎢
⎣⎢
2
4×ESR x V_FB
π×f_CO ×L x V_{OUT_}
⎤
⎥
⎦⎥
=
0dB
R_{F ×} 4 × ESR x V_{FB = 1}
R₁ 2π × f_CO × L x V_{OUT_}
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