MAX15022_11 Datasheet, PDF (20/28 Pages) Maxim Integrated Products – Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Dual LDO Controllers

Dual, 4A/2A, 4MHz, Step-Down DC-DC
Regulator with Dual LDO Controllers
Solving for R₁:
R₁
[kΩ]
=
R_F[kΩ]× 4 × ESR[mΩ]× V_FB [V]
2π × f_CO[kHz]× L[µH]× V_{OUT_} [V]
where V_FB is the 0.6V (typ) FB_ input-voltage set-point,
L is the value of the regulator inductor, ESR is the
series resistance of the output capacitor, and V_{OUT_} is
the desired output voltage.
1) C_F is determined from the compensator’s leading
zero, f_Z1, and R_F as follows:
C_F [µF]
=
2π
×
1
R_F[kΩ]× f_Z1[kHz]
2) C_CF is determined from the compensator’s high-fre-
quency pole, f_P1, and R_F as follows:
C_CF
[µF]
=
2π
×
R_F
1
[kΩ]
×
f_P1[kHz]
3) Calculate R₂ using the following equation:
R₂
[kΩ]
=
R₁[kΩ]
×
V_FB
V_{OUT_} [V]
[V]
− V_FB
[V]
where V_FB = 0.6V (typ) and V_{OUT_} is the output voltage
of the regulator.
Type III: Compensation when f_CO < f_ESR
As indicated above, the position of the output capaci-
tor’s inherent ESR zero is critical in designing an appro-
priate compensation network. When low-ESR ceramic
output capacitors (MLCCs) are used, the ESR zero fre-
quency (f_ESR) is usually much higher than the desired
crossover frequency (f_CO). In this case, a Type III com-
pensation network is recommended (see Figure 6a).
As shown in Figure 6b, the Type III compensation net-
work introduces two zeros and three poles into the con-
trol loop. The error amplifier has a low-frequency pole
at the origin, two zeros, and two higher frequency poles
at the following frequencies:
f_Z1
=
2π
1
× R_F
×
C_F
f_Z2
=
2π × C_I
1
× (R₁
+ R_I)
Two midband zeros (f_Z1 and f_Z2) are designed to com-
pensate for the pair of complex poles introduced by the
LC filter.
V_{OUT_}
C_CF
R_I
R1
C_I
R2
R_F
C_F
FB_
VREF
COMP_
Figure 6a. Type III Compensation Network
GAIN
(dB)
1ST ASYMPTOTE
(ωR_IC_F)^-1
4TH ASYMPTOTE
( )RF
R_I
2ND ASYMPTOTE
( )RF -1
R₁
3RD ASYMPTOTE
(ωR_FC_I)^-1
5TH ASYMPTOTE
(R_IC_CF)^-1
1ST POLE
(AT ORIGIN)
1ST ZERO
(R_FC_F)^-1
2ND POLE
(R_IC_I)^-1
2ND ZERO
(R₁C_I)^-1
3RD POLE ^{ω (rad/sec)}
(R_FC_CF)^-1
Figure 6b. Type III Compensation Network Response
f_P1 introduces a pole at zero frequency (integrator) for
nulling DC output-voltage errors.
f_P1= at the origin (0Hz)
Depending on the location of the ESR zero (f_ESR), f_P2
can be used to cancel it, or to provide additional atten-
uation of the high-frequency output ripple.
f_P2
=
1
2π × R_I
× C_I
f_P3 attenuates the high-frequency output ripple.
( ) ^fP3
=
2π ×R_F
1
× C_F
C_CF
=
2π
× R_F
1
× ^CF
C_F
×
+
C_CF
C_CF
Since C_CF << C_F then:
f_P3
=
2π
1
× R_F × C_CF
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