MAX11661 Datasheet, PDF (23/28 Pages) Maxim Integrated Products – 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs

500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Supply Current vs. Sampling Rate
For applications requiring lower throughput rates, the
user can reduce the clock frequency (fSCLK) to lower
the sample rate. Figure 11 shows the typical supply
current (IVDD) as a function of sample rate (fS) for the
500ksps devices. The part operates in normal mode and
is never powered down. The user can also power down
the ADC between conversions by using the power-down
mode. Figure 12 shows for the 500ksps device that as
the sample rate is reduced, the device remains in the
power-down state longer and the average supply cur-
rent (IVDD) drops accordingly.
SUPPLY CURRENT vs. SAMPLING RATE
2.0
VDD = 3V
f_SCLK = VARIABLE
16 CYCLES/CONVERSIONS
1.5
1.0
0.5
0
0
100 200 300 400 500
SAMPLING RATE (ksps)
SUPPLY CURRENT vs. SAMPLING RATE
1.5
VDD = 3V
f_SCLK = 8MHz
1.0
0.5
0
0 20 40 60 80 100 120 140 160
SAMPLING RATE (ksps)
Figure 11. Supply Current vs. Sample Rate (Normal Operating
Mode)
Figure 12. Supply Current vs. Sample Rate (Device Powered
Down Between Conversions)
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