MAX11661 Datasheet, PDF (22/28 Pages) Maxim Integrated Products – 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs

500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DOUT
HIGH
IMPEDANCE
INVALID
DATA
INVALID DATA OR HIGH IMPEDANCE
Figure 8. Entering Power-Down Mode
HIGH IMPEDANCE
CS
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DOUT
HIGH
IMPEDANCE
INVALID DATA (DUMMY CONVERSION)
HIGH
IMPEDANCE
VALID DATA
HIGH
IMPEDANCE
Figure 9. Exiting Power-Down Mode
OUTPUT CODE
111...111
111...110
111...101
FS - 1.5 x LSB
000...010
000...001
000...000
0123
2ⁿ-2 2ⁿ-1 2ⁿ
ANALOG
INPUT (LSB)
FULL SCALE (FS):
AIN1/AIN2 = REF (TDFN, µMAX)
AIN = V_DD (SOT23)
n = RESOLUTION
Figure 10. ADC Transfer Function
To remain in normal mode, keep CS low until the falling
edge of the 10th SCLK cycle. Pulling CS high after the
10th SCLK falling edge keeps the part in normal mode.
However, pulling CS high before the 10th SCLK falling
edge terminates the conversion, DOUT goes into high-
impedance mode, and the device enters power-down
mode. See Figure 8.
Power-Down Mode
In power-down mode, all bias circuitry is shut down
drawing typically only 1.3FA of leakage current. To save
power, put the device in power-down mode between
conversions. Using the power-down mode between
conversions is ideal for saving power when sampling the
analog input infrequently.
Entering Power-Down Mode
To enter power-down mode, drive CS high between the
2nd and 10th falling edges of SCLK (see Figure 8). By
pulling CS high, the current conversion terminates and
DOUT enters high impedance.
Exiting Power-Down Mode
To exit power-down mode, implement one dummy con-
version by driving CS low for at least 10 clock cycles
(see Figure 9). The data on DOUT is invalid during this
dummy conversion. The first conversion following the
dummy cycle contains a valid conversion result.
The power-up time equals the duration of the dummy
cycle, and is dependent on the clock frequency. The
power-up time for 500ksps operation (8MHz SCLK) is 2Fs.
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