MAX11661 Datasheet, PDF (21/28 Pages) Maxim Integrated Products – 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs

500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
To sustain the maximum sample rate, all devices have to
be resampled immediately after the 16th clock cycle. For
lower sample rates, the CS falling edge can be delayed
leaving DOUT in a high-impedance condition. Pull CS
high after the 10th SCLK falling edge (see the Operating
Modes section).
Analog Input
The devices produce a digital output that corresponds to
the analog input voltage within the specified operating
range of 0V to VREF for the dual-channel devices and 0V
to VDD for the single-channel devices.
Figure 6 shows an equivalent circuit for the analog input
AIN (for single-channel devices) and AIN1/AIN2 (for
dual-channel devices). Internal protection diodes D1/D2
confine the analog input voltage within the power rails
(VDD, GND). The analog input voltage can swing from
GND - 0.3V to VDD + 0.3V without damaging the device.
The electric load presented to the external stage driv-
ing the analog input varies depending on which mode
the ADC is in: track mode vs. conversion mode. In track
mode, the internal sampling capacitor CS (16pF) has to
be charged through the resistor R (R = 50I) to the input
voltage. For faithful sampling of the input, the capacitor
voltage on CS has to settle to the required accuracy dur-
ing the track time.
AIN1/AIN2
AIN
V_DD
SWITCH CLOSED IN TRACK MODE
SWITCH OPEN IN CONVERSION MODE
D1
R
CS
CP
D2
Figure 6. Analog Input Circuit
The source impedance of the external driving stage in
conjunction with the sampling switch resistance affects
the settling performance. The THD vs. Input Resistance
graph in the Typical Operating Characteristics shows
THD sensitivity as a function of the signal source imped-
ance. Keep the source impedance at a minimum for
high-dynamic-performance applications. Use a high-
performance op amp such as the MAX4430 to drive the
analog input, thereby decoupling the signal source and
the ADC.
While the ADC is in conversion mode, the sampling
switch is open presenting a pin capacitance, CP (CP
= 5pF), to the driving stage. See the Applications
Information section for information on choosing an
appropriate buffer for the ADC.
ADC Transfer Function
The output format is straight binary. The code transi-
tions midway between successive integer LSB values
such as 0.5 LSB, 1.5 LSB, etc. The LSB size for single-
channel devices is VDD/2ⁿ and for dual-channel devices
is VREF/2^n, where n is the resolution. The ideal transfer
characteristic is shown in Figure 10.
Operating Modes
The ICs offer two modes of operation: normal mode and
power-down mode. The logic state of the CS signal
during a conversion activates these modes. The power-
down mode can be used to optimize power dissipation
with respect to sample rate.
Normal Mode
In normal mode, the devices are powered up at all times,
thereby achieving their maximum throughput rates.
Figure 7 shows the timing diagram of these devices in
normal mode. The falling edge of CS samples the analog
input signal, starts a conversion, and frames the serial-
data transfer.
KEEP CS LOW UNTIL AFTER THE 10TH SCLK FALLING EDGE
CS
PULL CS HIGH AFTER THE 10TH SCLK FALLING EDGE
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DOUT
HIGH
IMPEDANCE
Figure 7. Normal Mode
VALID DATA
HIGH
IMPEDANCE
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