MAX11661 Datasheet, PDF (20/28 Pages) Maxim Integrated Products – 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs

500ksps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Detailed Description
The MAX11661–MAX11666 are fast, 12-/10-/8-bit, low-
power, single-supply ADCs. The devices operate from
a 2.2V to 3.6V supply and consume only 2.98mW
(VDD = 2.2V) or 4.37mW (VDD = 3V). These devices
are capable of sampling at full rate when driven by
an 8MHz clock. The dual-channel devices provide a
separate digital supply input (OVDD) to power the digi-
tal interface enabling communication with 1.5V, 1.8V,
2.5V, or 3V digital systems.
The conversion result appears at DOUT, MSB first, with a
leading zero followed by the 12-bit, 10-bit, or 8-bit result.
A 12-bit result is followed by two trailing zeros, a 10-bit
result is followed by four trailing zeros, and an 8-bit result
is followed by six trailing zeros. See Figures 1 and 5.
The dual-channel devices feature a dedicated refer-
ence input (REF). The input signal range for AIN1/AIN2
is defined as 0V to VREF with respect to AGND. The
single-channel devices use VDD as the reference. The
input signal range of AIN is defined as 0V to VDD with
respect to GND.
These ADCs include a power-down feature allowing
minimized power consumption at 2.5FA/ksps for lower
throughput rates. The wake-up and power-down feature
is controlled by using the SPI interface as described in
the Operating Modes section.
Serial Interface
The devices feature a 3-wire serial interface that directly
connects to SPI, QSPI, and MICROWIRE devices without
external logic. Figures 1 and 5 show the interface sig-
nals for a single conversion frame to achieve maximum
throughput.
The falling edge of CS defines the sampling instant.
Once CS transitions low, the external clock signal
(SCLK) controls the conversion.
The SAR core successively extracts binary-weighted bits
in every clock cycle. The MSB appears on the data bus
during the 2nd clock cycle with a delay outlined in the
timing specifications. All extracted data bits appear suc-
cessively on the data bus with the LSB appearing during
the 13th/11th/9th clock cycle for 12-/10-/8-bit operation.
The serial data stream of conversion bits is preceded by
a leading “zero” and succeeded by trailing “zeros.” The
data output (DOUT) goes into a high-impedance state
during the 16th clock cycle.
SAMPLE
SAMPLE
CS
SCLK
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
DOUT
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
HIGH
HIGH
IMPEDANCE
IMPEDANCE
SAMPLE
SAMPLE
CS
SCLK
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
DOUT
HIGH
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0 _HIGH
IMPEDANCE
IMPEDANCE
Figure 5. 10-/8-Bit Timing Diagrams
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