English
Language : 

MAX1108 Datasheet, PDF (16/20 Pages) Maxim Integrated Products – Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs
Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
to the SCLK pin; varying the analog input alters the
result of conversion that is clocked out at the DOUT pin.
A total of 10 clock cycles is required per conversion.
Data Framing
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte.
Acquisition starts on the falling edge of the fourth SCLK
and lasts for two SCLKs in external clock mode or four
SCLKs in internal clock mode. Conversion starts imme-
diately after acquisition is completed. The start bit is
defined as:
The first high bit clocked into DIN with CS
low any time the converter is idle; e.g., after
VDD is applied.
OR
In external clock mode, the first high bit
clocked into DIN after the bit 5 (D5) of a con-
version in progress is clocked onto the
DOUT pin.
OR
In internal clock mode, the first high bit
clocked into DIN after the bit 4 (D4) is
clocked onto the DOUT pin.
The MAX1108/MAX1109 can run at a maximum speed
of 10 clocks per conversion. Figure 10 shows the serial-
interface timing necessary to perform a conversion
every 10 SCLK cycles in external clock mode.
Many microcontrollers require that conversions occur in
multiples of 8 SCLK clocks; 16 clocks per conversion is
typically the fastest that a microcontroller can drive the
MAX1108/MAX1109. Figure 11 shows the serial-inter-
face timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
CS
SCLK
DIN
DOUT
A/D STATE
1
8 10 1
10 1
10 1
S CONTROL BYTE 0
tACQ
IDLE
S
CONTROL BYTE 1
CONVERSION RESULT 0
D7 D5
D0
tCONV
tACQ
S
CONTROL BYTE 2
S
CONVERSION RESULT 1
D7 D5
D0
D7
tCONV
tACQ
tCONV
Figure 10. Continuous Conversion, External Clock Mode, 10 Clocks/Conversion Timing
CS
SCLK
DIN
DOUT
1
8
17
25
S CONTROL BYTE 0
S
CONVERSION RESULT 0
D7
D0
CONTROL BYTE 1
S
CONVERSION RESULT 1
D7
D0
Figure 11. Continuous Conversion, External Clock Mode, 16 Clocks/Conversion Timing
16 ______________________________________________________________________________________