MAX1108 Datasheet, PDF (12/20 Pages) Maxim Integrated Products – Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs

Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
The serial interface provides easy connection to micro-
controllers with SPI, QSPI and MICROWIRE serial inter-
faces at clock rates up to 2MHz. For SPI and QSPI, set
CPOL = CPHA = 0 in the SPI control registers of the
microcontroller. Figure 5 shows the MAX1108/MAX1109
common serial-interface connections.
Digital Inputs
The logic levels of the MAX1108/MAX1109 digital input
are set to accept voltage levels from both +3V and +5V
systems, regardless of the supply voltages. Input data
(control byte) is clocked in at the DIN pin on the rising
edge of serial clock (SCLK). CS is the standard chip-
select signal which enables communication with the
device. SCLK is used to clock data in and out of serial
interface. In external clock mode, SCLK also sets the
conversion speed.
Digital Output
Output data is read on the rising edge of SCLK at
DOUT, MSB first (D7). In unipolar input mode, the out-
put is straight binary. For bipolar input mode, the output
is twos-complement (see Transfer Function section).
I/O
SCK
MISO
MOSI
+3V
SS
a) SPI
CS
SCK
MISO
MOSI
+3V
SS
b) QSPI
CS
SCLK
DOUT
DIN
MAX1108
MAX1109
CS
SCLK
DOUT
DIN
MAX1108
MAX1109
I/O
CS
SK
SCLK
SI
DOUT
SO
DIN
c) MICROWIRE
MAX1108
MAX1109
Figure 5. Common Serial-Interface Connections
DOUT is active when CS is low and high impedance
when CS is high. DOUT does not accept external volt-
ages greater than V_DD. In external-clock mode, data is
clocked out at the maximum clock rate of 500kHz while
conversion is in progress. In internal-clock mode, data
can be clocked out at up to 2MHz clock rate.
Modes of Operation
The MAX1108/MAX1109 feature single-ended or pseu-
do-differential operation in unipolar or bipolar configu-
ration. The device is programmed through the input
control-byte at the DIN pin of the serial interface
(Table 1). Table 2 shows the analog-input configuration
and Table 3 shows the input-voltage ranges in unipolar
and bipolar configuration.
How to Start a Conversion
A conversion is started by clocking a control byte into
DIN. With CS low, each rising edge on SCLK clocks a
bit from DIN into the MAX1108/MAX1109’s internal shift
register. After CS falls, the first arriving logic “1” bit at
DIN defines the MSB of the control byte. Until this first
start bit arrives, any number of logic “0” bits can be
clocked into DIN with no effect. Table 1 shows the con-
trol-byte format.
Using the Typical Operating Circuit (Figure 3), the sim-
plest software interface requires two 8-bit transfers to
perform a conversion (one 8-bit transfer to configure
the ADC, and one 8-bit transfer to clock out the 8-bit
conversion result). Figure 6 shows a single-conversion
timing diagram using external clock mode.
Clock Modes
The MAX1108/MAX1109 can use either an external ser-
ial clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the devices. Bit
3 of control-byte (I/ECLK) programs the clock mode.
Figure 8 shows the timing characteristics common to
both modes.
External Clock
In external clock mode, the external clock not only
shifts data in and out, it also drives the analog-to-digital
conversion steps. In this mode the clock frequency
must be between 50kHz and 500kHz. Single-conver-
sion timing using an external clock begins with a falling
edge on CS. When this occurs, DOUT leaves the high
impedance state and goes low. The first “1” clocked
into DIN by SCLK after CS is set low is considered as
the start bit. The next seven clocks latch in the rest of
the control byte. On the falling edge of the fourth clock,
track mode is enabled, and on the falling edge of the
sixth clock, acquisition is complete and conversion is
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