MAX1108 Datasheet, PDF (15/20 Pages) Maxim Integrated Products – Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs

Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
CS does not need to be held low once a conversion is
started. Pulling CS high prevents data from being
clocked into the MAX1108/MAX1109 and three-states
DOUT, but it does not adversely affect an internal
clock-mode conversion already in progress. In this
mode, data can be shifted in and out of the
MAX1108/MAX1109 at clock rates up to 2MHz, provid-
ed that the minimum acquisition time (t_ACQ) is kept
above 1µs.
Quick Look
To quickly evaluate the MAX1108/MAX1109’s analog
performance, use the circuit of Figure 9. The device
requires a control byte to be written to DIN before each
conversion. Tying CS to GND and DIN to V_DD feeds in
control bytes of FFH. In turn, this triggers single-ended,
unipolar conversions on CH0 in relation to COM in
external clock mode without powering down between
conversions. Apply an external 50kHz to 500kHz clock
CS
SCLK
DIN
DOUT
1
4
8
SEL2
SEL0
SEL1
I/EREF I/ECLK
REF
SHDN
SHDN
START
10
14
18
D7 D6 D5 D4 D3 D2 D1 D0
t_ACQ
t_CONV
A/D STATE
IDLE
IDLE
35µs MAX
Figure 8. Single Conversion Timing, Internal Clock Mode
V_DD
0.1µF
V_SUPPLY
1µF
ANALOG
INPUT _0.01µF
C1
1µF
MAX1108
GND
MAX1109
CH0
CS
SCLK
COM
DIN
DOUT
REF
500kHz
V_DD
OSCILLATOR
OSCILLOSCOPE
MSB
LSB
5µs/div
CH1
CH2
DOUT*
SCLK
*CONVERSION RESULT = 10101010
Figure 9. Quick-Look Schematic
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