MAX1108 Datasheet, PDF (11/20 Pages) Maxim Integrated Products – Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs

Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
holding capacitor C_HOLD through R_IN. At the end of
acquisition the T/H switch opens and C_HOLD is con-
nected to COM, retaining charge on C_HOLD as a sam-
ple of the signal at CH0, and the difference between
CH0 and COM is the converted signal. Once conver-
sion is complete, the T/H returns immediately to its
tracking mode. This procedure holds for the different
combinations summarized in Table 2.
The time available for the T/H to acquire an input signal
(t_ACQ) is determined by the clock frequency, and is 1µs
at the maximum clock frequency of 2MHz. The acquisi-
tion time is also the minimum time needed for the signal
to be acquired. It is calculated by:
t_ACQ = 6(R_S + R_IN)18pF
where R_IN = 6.5kΩ, R_S = the source impedance of
the input signal, and t_ACQ is never less than 1µs.
Note that source impedances below 2.7kΩ do not
significantly affect the AC performance of the ADC at
the maximum clock speed. If the input-source imped-
ance is higher than 3kΩ, the clock speed must be
reduced accordingly.
Pseudo-Differential Input
The MAX1108/MAX1109 input configuration is pseudo-
differential to the extent that only the signal at the sam-
pled input (SI) is stored in the holding capacitor
(C_HOLD). The reference input (RI) must remain stable
within ±0.5LSB (±0.1LSB for best results) in relation to
GND during a conversion. Sampled input and refer-
ence input configuration is determined by bit6–bit4
(SEL2–SEL0) of the control byte (Table 2).
If a varying signal is applied at the selected reference
input, its amplitude and frequency need to be limited.
The following equations determine the relationship
between the maximum signal amplitude and its fre-
quency to maintain ±0.5LSB accuracy:
Assuming a sinusoidal signal at the reference input
v_RI = V_RIsin(2πft)
the maximum voltage variation is determined by:
max ^dvRI
dt
= 2πf ⋅ v_RI ≤
1 LSB
t _CONV
=
V_REF
2⁸ t_CONV
a 60Hz signal at RI with an amplitude of 1.2V will gener-
ate a ±0.5LSB of error. This is with a 35µs conversion
time (maximum t_CONV in internal conversion mode) and
a reference voltage of +4.096V. When a DC reference
voltage is used at RI, connect a 0.1µF capacitor to
GND to minimize noise at the input.
The input configuration selection also determines
unipolar or bipolar conversion mode. The common-
mode input range of CH0, CH1, and COM is 0 to +V_DD.
In unipolar mode, full scale is achieved when (SI - RI) =
V_REF; in bipolar mode, full scale is achieved when _(SI
- RI)_ = V_REF / 2. In unipolar mode, SI must be higher
than RI; in bipolar mode, SI can span above and below
RI provided that it is within the common-mode range.
Conversion Process
The comparator negative input is connected to the auto-
zero rail. Since the device requires only a single supply,
the ZERO node at the input of the comparator equals
V_DD/2. The capacitive DAC restores node ZERO to have
0V difference at the comparator inputs within the limits
of 8-bit resolution. This action is equivalent to transfer-
ring a charge of 18pF(V_IN+ - V_IN-) from C_HOLD to the
binary-weighted capacitive DAC which, in turn, forms a
digital representation of the analog-input signal.
Input Voltage Range
Internal protection diodes that clamp the analog input
to V_DD and AGND allow the channel input pins (CH0,
CH1, and COM) to swing from (AGND - 0.3V) to (V_DD +
0.3V) without damage. However, for accurate conver-
sions, the inputs must not exceed (V_DD + 50mV) or be
less than (GND - 50mV).
If the analog input voltage on an “off” channel
exceeds 50mV beyond the supplies, the current
should be limited to 2mA to maintain conversion
accuracy on the “on” channel.
The MAX1108/MAX1109 input range is from 0 to V_DD;
unipolar or bipolar conversion is available. In unipolar
mode, the output code is invalid (code zero) when a
negative input voltage (or a negative differential input
voltage) is applied. The reference input-voltage range
at REF is from 1V to (V_DD + 50mV.)
Input Bandwidth
The ADC’s input tracking circuitry has a 1.5MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Serial Interface
The MAX1108/MAX1109 have a 4-wire serial interface.
The CS, DIN, and SCLK inputs are used to control the
device, while the three-state DOUT pin is used to
access the result of conversion.
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