MAX1108 Datasheet, PDF (14/20 Pages) Maxim Integrated Products – Single-Supply, Low-Power, 2-Channel, Serial 8-Bit ADCs

Single-Supply, Low-Power,
2-Channel, Serial 8-Bit ADCs
initiated. The MSB successive-approximation bit deci-
sion is made on the rising edge of the seventh SCLK.
On the falling edge of the eighth SCLK, the MSB is
clocked out on the DOUT pin; on each of the next
seven SCLK falling edges, the remaining bits of conver-
sion are clocked out. Zeros are clocked out on DOUT
after the LSB has been clocked out, until CS is dis-
abled. Then DOUT becomes high impedance and the
part is ready for another conversion (Figure 6).
The conversion must complete in 1ms, or droop on the
sample-and-hold capacitors may degrade conversion
results. Use internal clock mode if the serial-clock fre-
quency is less than 50kHz, or if serial-clock interrup-
tions could cause the conversion interval to exceed
1ms.
Internal Clock
Internal clock mode frees the µP from the burden of
running the SAR conversion clock. This allows the con-
version results to be read back at the processor’s con-
venience, at any clock rate up to 2MHz.
An internal register stores data when the conversion is
in progress. On the falling edge of the fourth SCLK,
track mode is enabled, and on the falling edge of the
eighth SCLK, acquisition is complete and internal con-
version is initiated. The internal 400kHz clock com-
pletes the conversion in 20µs typically (35µs max), at
which time the MSB of the conversion is present at the
DOUT pin. The falling edge of SCLK clocks the remain-
ing data out of this register at any time after the conver-
sion is complete (Figure 8).
CS
SCLK
DIN
DOUT
A/D STATE
1
4
8
12
16
MSB
LSB
REF
SEL2 SEL1 SEL0 I/ECLK I/EREF _SHDN SHDN
START
MSB
D7
D6
D5 D4
LSB
D3
D2 D1
D0
t_ACQ
IDLE
t_CONV
Figure 6. Single Conversion Timing, External Clock Mode
20
IDLE
CS
SCLK
DIN
DOUT
t_CSS
t_CSH
t_DS
t_DH
t_DV
•••
t_CH
t_CL
•••
•••
•••
t_CSH
t_DO
t_TR
Figure 7. Detailed Serial-Interface Timing
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