MAX1219 Datasheet, PDF (15/21 Pages) Maxim Integrated Products – 1.8V, Dual, 12-Bit, 210Msps ADC for Broadband Applications

1.8V, Dual, 12-Bit, 210Msps ADC for
Broadband Applications
Table 1. MAX1219 Digital Output Coding
INAP/INBP
ANALOG INPUT
VOLTAGE LEVEL
INAN/INBN
ANALOG INPUT
VOLTAGE LEVEL
OUT-OF-RANGE
ORAP/ORBP
(ORAN/ORBN)
> V_CM + V_FS / 4
V_CM + V_FS / 4
V_CM
V_CM - V_FS / 4
< V_CM + V_FS / 4
< V_CM - V_FS / 4
V_CM - V_FS / 4
V_CM
V_CM + V_FS / 4
> V_CM - V_FS / 4
1 (0)
0 (1)
0 (1)
0 (1)
1 (0)
BINARY DIGITAL
OUTPUT CODE
(DA11P/N–DA0P/N;
DB11P/N–DB0P/N)
1111 1111 1111
(exceeds +FS, OR set)
1111 1111 1111 (+FS)
1000 0000 0000 or
0111 1111 1111 (FS / 2)
0000 0000 0000 (-FS)
0000 0000 0000
(exceeds -FS, OR set)
TWO’S-COMPLEMENT
DIGITAL OUTPUT CODE
(DA11P/N–DA0P/N;
DB11P/N–DB0P/N)
0111 1111 1111
(exceeds +FS, OR set)
0111 1111 1111 (+FS)
0000 0000 0000 or
1111 1111 1111 (FS / 2)
1000 0000 0000 (-FS)
1000 0000 0000
(exceeds -FS, OR set)
the SNR performance. To accomplish this, AC-couple a
50Ω reverse-terminated clock signal source with low
phase noise into a fast differential receiver, such as the
MAX9388 (Figure 7). The receiver produces the neces-
sary LVPECL output levels to drive the clock inputs of
the data converter.
Transformer-Coupled, Differential
Analog Input Drive
The MAX1219 provides the best SFDR and THD perfor-
mance with fully differential input signals. In differential input
mode, even-order harmonics are lower since the inputs to
each channel (INAP/N and INBP/N) are balanced, and
each of the channel’s inputs only requires half the signal
swing compared to a single-ended configuration.
Wideband RF transformers provide an excellent solu-
tion to convert a single-ended signal to a fully differen-
tial signal. Apply a secondary-side termination to a 1:1
transformer (e.g., Mini-Circuit’s ADT1-1WT) by two sep-
arate 24.9Ω resistors. Higher source impedance values
can be used at the expense of a degradation in dynam-
ic performance. Use resistors with tight tolerance
(0.5%) to minimize effects of imbalance, maximizing the
ADC’s dynamic range. This configuration optimizes
THD and SFDR performance of the ADC by reducing
the effects of transformer parasitics. However, the
source impedance combined with the shunt capaci-
tance provided by a PC board and the ADC’s parasitic
capacitance limit the ADC’s full-power input bandwidth.
To further enhance THD and SFDR performance at high
input frequencies (> 100MHz) place a second trans-
former (Figure 8) in series with the single-ended-to-differ-
ential conversion transformer. The second transformer
reduces the increase of even-order harmonics at high
frequencies.
Single-Ended, AC-Coupled Analog Inputs
Although not recommended, the MAX1219 can be used
in single-ended mode (Figure 9). AC-couple the analog
signals to the positive input of each channel (INAP,
INBP) through a 0.1µF capacitor terminated with a 49.9Ω
resistor to AGND. Terminate the negative input of each
channel (INAN, INBN) with a 24.9Ω resistor in series with
a 0.1µF capacitor to AGND. In single-ended mode the
input range is limited to approximately half of the FSR of
the device, and dynamic performance usually degrades.
Grounding, Bypassing, and
Board Layout
The MAX1219 requires board layout design techniques
suitable for high-speed data converters. This ADC
accepts separate analog and output power supplies. The
analog and output power-supply inputs accept 1.71V to
1.89V input voltage ranges. Although both AV_CC and
OV_CC can be supplied from one source, use separate
sources to reduce performance degradation caused by
output switching currents, which can couple into the ana-
log supply network. Isolate analog and output supplies
(AV_CC and OV_CC) where they enter the PC board with
separate networks of ferrite beads and capacitors to their
corresponding grounds (AGND, OGND).
To achieve optimum performance, provide each supply
with a separate network of 47µF tantalum capacitor and
parallel combination of 10µF and 1µF ceramic capaci-
tors. Additionally, the ADC requires each supply input
to be bypassed with a separate 0.1µF ceramic capaci-
tor (Figure 10). Locate these capacitors directly at the
ADC supply inputs or as close as possible to the
MAX1219. Choose surface-mount capacitors, whose
preferred location is on the same side as the converter
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