MAX1219 Datasheet, PDF (12/21 Pages) Maxim Integrated Products – 1.8V, Dual, 12-Bit, 210Msps ADC for Broadband Applications

1.8V, Dual, 12-Bit, 210Msps ADC for
Broadband Applications
AV_CC
IN_P
C_P
1kΩ
1kΩ
IN_N
C_P
C_S IS THE SAMPLING CAPACITANCE
C_P IS THE PARASITIC CAPACITANCE ~ 1pF
IN_P
V_CM
IN_N
GND
IN_P - IN_N
T/H
C_S
C_S
MAX1219
12-BIT PIPELINE
ADC
FROM CLOCK-MANAGEMENT BLOCK
TO COMMON MODE
V_CM + V_FS / 4
V_CM - V_FS / 4
+V_FS / 2
GND
Figure 2. Simplified Analog Input Architecture and Allowable Input Voltage Range
-V_FS / 2
Divide-by-2 Clock Control
The MAX1219 offers a clock control line (CLKDIV) that
supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at one-
half the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that require this divide-by-2 mode. Connecting CLKDIV
to OV_CC disables the divide-by-2 mode.
System Timing Requirements
Figure 5 depicts the relationship between the clock
input and output, analog input, sampling event, and
data output. The MAX1219 samples on the rising
(falling) edge of CLKP (CLKN). Output data is valid on
the next rising (falling) edge of DCOP (DCON), with an
internal latency of 11 clock cycles.
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