MAX1219 Datasheet, PDF(14/21 Page) Maxim Integrated Products – 1.8V, Dual, 12-Bit, 210Msps ADC for Broadband Applications

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MAX1219 Datasheet, PDF (14/21 Pages) Maxim Integrated Products – 1.8V, Dual, 12-Bit, 210Msps ADC for Broadband Applications

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1.8V, Dual, 12-Bit, 210Msps ADC for

Broadband Applications

CLKP

CLKN

AVDD

2.89kâ¦

5.35kâ¦

AGND

Figure 4. Simplified Clock Input Architecture

The MAX1219 offers an additional set of differential out-

put pairs (ORAP/N and ORBP/N) to flag out-of-range

conditions for each channel, where out-of-range is

above positive or below negative full scale. An out-of-

range condition on each channel is identified with ORAP

or ORBP (ORAN or ORBN) transitioning high (low).

Note: Although a differential LVDS output architecture

reduces single-ended transients to the supply and

ground planes, capacitive loading on the digital out-

puts should still be kept as low as possible. Using

LVDS buffers on the digital outputs of the ADC when

driving larger loads improves overall performance and

reduces system-timing constraints.

Applications Information

FSR Adjustments Using the Internal

Bandgap Reference

The MAX1219 supports a 10% (Â±5%) full-scale adjust-

ment range on each channel. Add an external resistor

ranging from 13kâ¦ to 1Mâ¦ between the reference

adjust input of the channel (REFADJA, REFADJB) and

AGND to decrease the full-scale range of the channel.

Adding a variable resistor, potentiometer, or predeter-

mined resistor value between the reference adjust input

of a channel (REFADJA, REFADJB) and its respective

reference input/output (REFA, REFB) increases the FSR

of the channel. Figure 6a shows the two possible con-

figurations and their impact on the overall full-scale

range adjustment of the MAX1219. The FSR for each

channel can be set to any value in the allowed range

independent of the FSR of the other channel. Do not

use resistor values of less than 13kâ¦ to avoid instability

of the internal gain regulation loop for the bandgap ref-

erence. See Figure 6b for the resulting FSR for a series

of resistor values.

Differential, AC-Coupled, LVPECL-

Compatible Clock Input

The MAX1219 dynamic performance depends on the

use of a very clean clock source. The phase noise floor

of the clock source has a negative impact on the SNR

performance. Spurious signals on the clock signal

source also affect the ADCâs dynamic range. The pre-

ferred method of clocking the MAX1219 is differentially

with LVDS- or LVPECL-compatible input levels. The fast

data transition rates of these logic families minimize the

clock input circuitryâs transition uncertainty improving

INAN/INBN

SAMPLING EVENT

INAP/INBP

CLKN

CLKP

DCON

DCOP

DA0P/NâDA11P/N

DB0P/NâDB11P/N

tAD

tCPDL

N - 11

tPDL

N - 11

N+1

N - 10

tLATENCY

N - 10

SAMPLING EVENT

N -1

N + 11

tCH

tCL

N + 12

N+1

Figure 5. System and Output Timing Diagram

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