MAX14811 Datasheet, PDF (14/20 Pages) Maxim Integrated Products – Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers with Fault Condition Management

MAX14811
Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers
with Fault Condition Management
f_IN = f_{INN_} = f_{INP_}
where f_{INN_} and f_{INP_} are the switching frequencies of
the inputs INN_ and INP_, respectively, and where BRF
is the burst repetition frequency and BTD is the burst
time duration. The typical value of the gate capacitances
of the power FET are C_N = 0.2nF, C_P = 0.4nF. For an
output load that has a resistance of R_L and capacitance
of C_L, the power dissipation can be estimated as follows
(assume square-wave output and neglect the resistance
of the switches):
( ) P_{VPP_}
= _(C_O + C_L ) × f_IN ×
V_{PP_}
− V_{NN_}

2
+


V_{PP_}
 R_L
2
× ^{1} ×( BRF × BTD)
2
where C_O is the device’s output capacitance.
Power Supplies and Bypassing
The device operates from independent supply voltage
sets (only V_DD and V_SS are common to both channels).
The logic input circuit operates from a +2.7V to +6V
single supply (V_DD). The level-shift driver dual supplies,
V_{CC_}/V_{EE_} operate from Q4.75V to Q12.6V.
The V_{PP_}/V_{NN_} high-side and low-side supplies are
driven from a single positive supply up to +220V, from a
single negative supply up to -200V, or from Q110V dual
supplies. Either V_{PP_} or V_{NN_} can be set at 0V. Bypass
each supply input to ground with a 0.1FF capacitor as
close as possible to the device.
Depending on the load of the pulser, additional bypass-
ing may be needed to keep the output of V_{PP_} and
V_{NN_} stable during output transitions. For example, with
C_OUT = 100pF and R_OUT = 100I load, additional 10FF
(typ) capacitor is recommended. V_SS is the substrate
voltage and must be connected to a voltage equal to or
more negative than the more negative voltage of V_NN1
or V_NN2.
Exposed Pad and Layout Concerns
The device provides an exposed pad (EP) underneath
the TQFN package for improved thermal performance.
The EP is internally connected to V_SS. Connect EP to
V_SS externally and do not run traces under the package
to avoid possible short circuits. To aid heat dissipation,
connect EP to a similarly sized pad on the component
side of the PCB. This pad should be connected through
to the solder-side copper by several plated holes to a
large heat-spreading copper area to conduct heat away
from the device.
The device’s high-speed pulser requires low-inductance
bypass capacitors to their supply inputs. High-speed
PCB trace design practices are recommended. Pay
particular attention to minimize trace lengths and use suf-
ficient trace width to reduce inductance. Use of surface-
mount components is recommended.
Supply Sequencing
V_SS must be lower than or equal to the more negative
voltage of V_NN1 or V_NN2 at all times. No other power-
supply sequencing is required for the device.
Typical Applications Circuit
Figure 7 shows the MAX14811 in a bipolar pulsing
application.
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