MAX14811 Datasheet, PDF (12/20 Pages) Maxim Integrated Products – Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers with Fault Condition Management

MAX14811
Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers
with Fault Condition Management
Detailed Description
The MAX14811 integrated circuit generates high-voltage,
high-frequency unipolar or bipolar pulses from low-volt-
age logic inputs. The dual pulser features independent
logic inputs, independent high-voltage pulser outputs
with active clamps, and independent high-voltage supply
inputs.
The device features fault condition management to pro-
tect the outputs. The outputs enter three-state if both
INP_ and INN_ are logic-high. The device has a 9I
output impedance for the high-voltage outputs and a
27I impedance for the active clamp. The high-voltage
outputs are guaranteed to provide 2.0A (typ) output
current. All the pulser outputs and clamp outputs have
overvoltage protection.
The device uses three logic inputs per channel to con-
trol the positive and negative pulses and active clamp.
Also included are two independent enable inputs.
Disabling EN_ ensures the output MOSFETs are not
accidentally turned on during fast power-supply ramp-
ing. This allows for faster ramp times and shorter delays
between pulsing modes. A low-power shutdown mode
reduces power consumption to less than 1FA. All digital
inputs are CMOS compatible.
Logic Inputs (INP_, INN_, INC_, EN_, SHDN)
The device has a total of nine logic-input signals. SHDN
controls the power-up and power-down of the device.
There are two sets of INP_, INN_, INC_, and EN_ signals:
one for each channel. Each INP_ and INN_ input has a
10kI (typ) pulldown resistor. INP_ controls the on and
off states of the high-side FET, INN_ controls the on and
off states of the low-side FET, INC_ controls the active
clamp, and EN_ controls the gate-to-source short. These
signals give complete control of the output stage of each
driver (see Table 1 for all logic combinations).
The device logic inputs are CMOS-logic-compatible and
the logic levels are referenced to V_DD for maximum flex-
ibility. The low 5pF (typ) input capacitance of the logic
inputs reduces loading and increases switching speed.
Table 1. Truth Table
SHDN
INPUTS
EN_ INP_ INN_ INC_
OP_
0
X
X
X
X
High
Impedance
1
0
X
X
X
High
Impedance
1
1
0
0
0
High
Impedance
1
1
0
0
1
High
Impedance
1
1
0
1
X
High
Impedance
1
1
1
0
X
V_{PP_}
1
1
1
1
X
High
Impedance
X = Don’t care, 0 = Logic-low, 1 = Logic-high.
OUTPUTS
ON_
High
Impedance
High
Impedance
High
Impedance
High
Impedance
V_{NN_}
High
Impedance
High
Impedance
OCP_, OCN_
High
Impedance
STATE
Power-down, INP_/INN_ disabled,
gate-source short disabled, clamp
disabled.
High
Impedance
Power-down, INP_/INN_ disabled,
gate-source short enabled, clamp
disabled.
High
Impedance
GND
High
Impedance
High
Impedance
High
Impedance
Power-up, all inputs enabled, gate-
source short disabled.
Power-up, all inputs enabled, gate-
source short disabled.
Power-up, all inputs enabled, gate-
source short disabled.
Power-up, all inputs enabled, gate-
source short disabled.
Fault condition if INP_ = 1 and
INN_ = 1 for more than 5.5ns.
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