MAX14811 Datasheet, PDF (13/20 Pages) Maxim Integrated Products – Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers with Fault Condition Management

MAX14811
Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers
with Fault Condition Management
High-Voltage Output Protection
The device’s high-voltage outputs feature an integrated
overvoltage protection circuit that allows the user to
implement multilevel pulsing by connecting the outputs
of multiple pulser channels in parallel. Internal diodes in
series with the ON_ and OP_ outputs prevent the body
diode of the high-side and low-side FETs from switching
on when a voltage greater than V_{NN_} or V_{PP_} is present
on the output. See the Functional Diagram.
Active Clamps
The device features an active clamp circuit to improve
pulse quality and reduce 2nd harmonic output. The
clamp circuit consists of an n-channel (DC-coupled) and
a p-channel (AC and DC delay coupled) high-voltage
FETs that are switched on or off by the logic clamp input
(INC_). The device features protected clamp devices,
allowing the clamp circuit to be used in bipolar pulsing
circuits (see the Functional Diagram and Figure 1). A
diode in series with the OCN_ output prevents the body
diode of the low-side FET from turning on when a voltage
lower than GND is present. Another diode in series with
the OCP_ output prevents the body diode of the high-
side FET from turning on when a voltage higher than
ground is present.
The user can connect the active clamp input (INC_) to
a logic-high voltage and drive only the INP_ and INN_
inputs to minimize the number of signals used to drive
the device. In this case, whenever both the INP_ and
INN_ inputs are low and the INC_ input is high, the active
clamp circuit pulls the output to GND through the OCP_
and OCN_ outputs (see Table 1 for more information).
Fault Protection
The device features fault protection management to
protect the outputs. When INP_ and INN_ are both logic-
high, the outputs (OP_, ON_, OCP_, and OCN_) enter a
high-Z state.
Power-Supply Ramping and Gate-Source
Short Circuit
The device includes a gate-source short circuit that is
controlled by the enable input (EN_). When SHDN is high
and EN_ is low, a 60I switch shorts together the gate
and source of the high-side output FET. At the same time,
a similar switch shorts the gate and source of the low-
side output FET (Table 1). The gate-source short circuit
prevents accidental turn-on of the output FETs due to the
ramping voltage on V_{PP_} and V_{NN_}, and allows for faster
ramping rates and smaller delay times between pulsing
modes.
Shutdown Mode
SHDN is common to both channel 1 and channel 2 and
powers up or down the device. Drive SHDN low to power
down all internal circuits (except the clamp circuits).
When SHDN is low, the device is in the lowest power
state (1FA) and the gate-source short circuit is disabled.
The device takes 1Fs (typ) to become active when SHDN
is disabled.
Thermal Protection
A thermal shutdown circuit with a typical threshold of
+150NC prevents damage due to excessive power
dissipation. When the junction temperature exceeds
T_J = +150NC, all outputs are disabled. Normal opera-
tion typically resumes after the IC’s junction temperature
drops below +130NC.
Applications Information
AC-Coupling Capacitor Selection
The value of all AC-coupling capacitors (between CDP_
and CGP_ and between CDN_ and CGN_) must be
between 1nF and 10nF. The voltage rating of the capaci-
tor must be at least as high as V_{PP_}. Place the capaci-
tors as close as possible to the device. Because INP_
and part of INC_ are AC-coupled to the output devices,
they cannot be driven high indefinitely when the device
is active.
Power Dissipation
The device’s power dissipation consists of three major
components caused by the current consumption from
V_{CC_}, V_{PP_}, and V_{NN_}. The sum of these components
(P_{VCC_}, P_{VPP_,} and P_{VNN_}) must be kept below the maxi-
mum power-dissipation limit. See the Typical Operating
Characteristics section for more information on typical
supply currents vs. switching frequencies. The device
consumes most of the supply current from V_{CC_} supply
to charge and discharge internal nodes such as the gate
capacitance of the high-side FET (C_P) and the low-side
FET (C_N). Neglecting the small quiescent supply current
and a small amount of current used to charge and dis-
charge the capacitances at the internal gate clamp FETs,
the power consumption can be estimated as follows:
P_{VCC_} = [(C_N × V_{CC_2} × f_IN) + (C_P × V_{CC_2} × f_IN)] ×
(BRF × BTD)
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