80220 Datasheet, PDF (41/91 Pages) LSI Computer Systems – 100BASE-TX/10BASE-T Ethernet Media Interface Adapter

80220/80221
Table 17. MI Register 17 (Configuration 2) Structure And Bit Definition
17.15
PLED3_1
R/W
17.14
PLED3_0
R/W
17.13
PLED2_1
R/W
17.12
PLED2_0
R/W
17.11
PLED1_1
R/W
17.10
PLED1_0
R/W
17.9
PLED0_1
R/W
17.8
PLED0_0
R/W
17.7
17.6
17.5
17.4
17.3
17.2
17.1
17.0
LED_DEF1 LED_DEF0 APOL_DIS JAB_DIS MREG INT_MDIO P26_CFG
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
17.15
17.14
Symbol
PLED3_1
PLED3_0
Name
Programmable LED
Output Select, Pin
PLED3
17.13 PLED2_1
17.12 PLED2_0
Programmable LED
Output Select, Pin
PLED2
17.11 PLED1_1
17.10 PLED1_0
Programmable LED
Output Select, Pin
PLED1
17.9 PLED0_1
17.8 PLED0_0
Programmable LED
Output Select, Pin
PLED0
17.7 LED_DEF1 LED Normal
17.6 LED_DEF0 Function Select
17.5 APOL_DIS Auto Polarity
Disable
17.4 JAB_DIS
Jabber Disable
Select
17.3 MREG
Multiple Register
Access Enable
17.2 INT_MDIO Interrupt Scheme
Select
17.1 R/J_CFG
R/J Configuration
Select
17.0
Definition
11 = Normal
10 = LED Blink
01 = LED On
00 = LED Off
11 = Normal
10 = LED Blink
01 = LED On
00 = LED Off
11 = Normal
10 = LED Blink
01 = LED On
00 = LED Off
11 = Normal
10 = LED Blink
01 = LED On
00 = LED Off
See Table 5
(PLED3 Is Determined By
Bits 17.7-17.6 And Table 5.
Default is LINK100)
(PLED3 Is Toggling 100 mS
Low, 100 mS High)
(PLED3 Is Low)
(PLED3 Is High)
(PLED2 Is Determined By
Bits 17.7-17.6 And Table 5.
Default is Activity)
(PLED2 Is Toggling 100 mS
Low, 100 mS High)
(PLED2 Is Low)
(PLED2 Is High)
(PLED1 Is Determined By
Bits 17.7-17.6 And Table 5.
Default is Full Duplex)
(PLED1 Is Toggling 100 mS
Low, 100 mS High)
(PLED1 Is Low)
(PLED1 Is High)
(PLED0 Is Determined By
Bits 17.7-17.6 And Table 5.
Default is LINK10)
(PLED0 Is Toggling 100 mS
Low, 100 mS High)
(PLED0 Is Low)
(PLED0 Is High)
1 = Auto Polarity Correction Function Disabled
0 = Normal
1 = Jabber Disabled
0 = Enabled
1 = Multiple Register Access Enabled
0 = No Multiple Register Access
1 = Interrupt Signaled With MDIO Pulse During Idle
0 = Interrupt Not Signalled On MDIO
1 = RX_EN/JAM Pin Is Configured To Be JAM
0 = RX_EN/JAM Pin Is Configured To Be RX_EN
Reserved
R/W Def.
R/W 11
R/W 11
R/W 11
R/W 11
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
44-411
MD400159/E