80220 Datasheet, PDF (31/91 Pages) LSI Computer Systems – 100BASE-TX/10BASE-T Ethernet Media Interface Adapter

80220/80221
this bit is set, an interrupt is signalled by an low going pulse
on MDIO when MDC is high and the serial port is in the idle
state, as shown in the timing diagram in Figure 10. Once
MDIO is forced low to indicate the interrupt condition,
MDIO stays low until MDC returns low. Once MDC returns
low, then MDIO goes back to high impedance state. If the
interrupt occurs while the serial port is being accessed,
then the MDIO interrupt pulse is delayed until one clock bit
after the serial port access cycle is ended as shown in
Figure 10.
a.) Interrupt Happens During Idle.
INTERNAL
INTERRUPT
MDC
MDIO
MDIO HI-Z
PULLED HIGH EXTERNALLY
INTERRUPT
PULSE
MDIO HI-Z
PULLED HIGH EXTERNALLY
b.) Interrupt Happens During Read Cycle.
INTERNAL
INTERRUPT
MDC
MDIO
B1
B0
LAST TWO BITS
OF READ CYCLE
INTERRUPT
PULSE
MDIO HI-Z
PULLED HIGH EXTERNALLY
MDIO HI-Z
PULLED HIGH EXTERNALLY
Figure 10. MDIO Interrupt Pulse
43-311
MD400159/E