80220 Datasheet, PDF (19/91 Pages) LSI Computer Systems – 100BASE-TX/10BASE-T Ethernet Media Interface Adapter

80220/80221
level MLT-3 digital data from the comparators and con-
verts it to back to normal digital data to be used for clock
and data recovery.
3.9.2 Receiver - 10 Mbps
The 10 Mbps receiver is able to detect input signals from
the twisted pair cable that are within the template shown in
Figure 5. The inputs are biased by internal resistors. The
TP inputs pass through a low pass filter designed to
eliminate any high frequency noise on the input. The
output of the receive filter goes to two different types of
comparators, squelch and zero crossing. The squelch
comparator determines whether the signal is valid, and the
zero crossing comparator is used to sense the actual data
transitions once the signal is determined to be valid. The
output of the squelch comparator goes to the squelch
circuit and is also used for link pulse detection, SOI
detection, and reverse polarity detection; the output of the
zero crossing comparator is used for clock and data
recovery in the Manchester decoder.
a. Short Bit
Slope 0.5 V/ns
3.1 V
585 mV
585 mV sin ( _* t/PW)
0
PW
b. Long Bit
Slope 0.5 V/ns
3.1 V
585 mV
585 mV sin (2 _* t/PW)
585 mV sin [2 (t – PW/2)/PW]
0
PW/4
3PW/4
PW
Figure 5. TP Input Voltage Template-10Mbps
3.9.3 TP Squelch - 100 Mbps
The squelch block determines if the TP input contains valid
data. The 100 Mbps TP squelch is one of the criteria used
to determine link intergrity. The squelch comparators
compare the TP inputs against fixed positive and negative
thresholds, called squelch levels. The output from the
squelch comparator goes to a digital squelch circuit which
determines if the receive input data on that channel is valid.
If the data is invalid, the receiver is in the squelched state.
If the input voltage exceeds the squelch levels at least 4
times with alternating polarity within a 10 µS interval, the
data is considered to be valid by the squelch circuit and the
receiver now enters into the unquelch state. In the
unsquelch state, the receive threshold level is reduced by
approximately 30% for noise immunity reasons and is
called the unsquelch level. When the receiver is in the
unsquelch state, then the input signal is deemed to be
valid. The device stays in the unsquelch state until loss of
data is detected. Loss of data is detected if no alternating
polarity unsquelch transitions are detected during any 10
µS interval. When the loss of data is detected, the receive
squelch is turned on again.
3.9.4 TP Squelch, 10 Mbps
The TP squelch algorithm for 10 Mbps mode is identical to
the 100 Mbps mode except, (1) the 10 Mbps TP squelch
algorithm is not used for link integrity but to sense the
beginning of a packet, (2) the receiver goes into the
unsquelch state if the input voltage exceeds the squelch
levels for three bit times with alternating polarity within a
50-250 nS interval, (3) the receiver goes into the squelch
state when idle is detected, (4) unsquelch detection has no
affect on link integrity, link pulses are used for that in 10
Mbps mode, (5) start of packet is determined when the
receiver goes into the unsquelch state and CRS is as-
serted, and (6) the receiver meets the squelch require-
ments defined in IEEE 802.3 Clause 14.
3.9.5 Equalizer Disable
The adaptive equalizer can be disabled by setting the
equalizer disable bit in the MI serial port Configuration 1
register. When disabled, the equalizer is forced into the
response it would normally have if zero cable length was
detected.
3.9.6 Receive Level Adjust
The receiver squelch and unsquelch levels can be lowered
by 4.5 dB by setting the receive level adjust bit in the MI
serial port Configuration 1 register. By setting this bit, the
device may be able to support longer cable lengths.
41-199
MD400159/E