80220 Datasheet, PDF (32/91 Pages) LSI Computer Systems – 100BASE-TX/10BASE-T Ethernet Media Interface Adapter

80220/80221
4.0 Register Description
Table 8. MI Serial Port Frame Structure
<Idle>
IDLE
<Start>
ST[1:0]
<Read>
READ
<Write>
WRITE
<PHY Addr.> <Reg. Addr.> <Turnaround> <Data>
PHYAD[4:0] REGAD[4:0]
TA[1:0] D[15:0]....
Register 0 Control
Register 1 Status
Register 2 PHY ID #1
Register 3 PHY ID #2
Register 4 AutoNegotiation Advertisement
Register 5 AutoNegotiation Remote End Capability
Register 16 Configuration 1
Register 17 Configuration 2
Register 18 Status Output
Register 19 Mask
Register 20 Reserved
Symbol
IDLE
Name
Idle Pattern
ST1
ST0
READ
WRITE
PHYAD[4:0]
REGAD4[4:0]
Start Bits
Read Select
Write Select
Physical Device
Address
Register Address
TA1
Turnaround Time
TA0
D[15:0]....
Data
IDLE is shifted in first
Definition
R/W
These bits are an idle pattern. Device will not initiate an
W
MI cycle until it detects at least 32 1's.
When ST[1:0]=01, a MI Serial Port access cycle starts.
W
1 = Read Cycle
W
1 = Write Cycle
W
When PHYAD[4:0]=MDA[4:0] pins inverted, the MI Serial
W
Port is selected for operation.
If REGAD[4:0]=00000-11110, these bits determine the
W
specific register from which D[15:0] is read/written. If multiple
register access is enabled and REGAD[4:0]=11111, all
registers are read/written in a single cycle.
These bits provide some turnaround time for MDIO
R/W
When READ=1, TA[1:0]=Z0
When WRITE=1, TA[1:0]=ZZ
These 16 bits contain data to/from one of the eleven registers Any
selected by register address bits REGAD[4:0].
32
MD400159/E