YMF721 Datasheet, PDF (19/41 Pages) LSI Computer Systems – FM + Wavetable Synthesizer LSI

YMF721
Data Register Array 1 (R/W)
Index
D7
D6
D5
00 - 01h
04h
-
-
05h
-
-
-
20 - 35h AM
VIB
EGT
40 - 55h
KSL
60 - 75h
AR
80 - 95h
SL
A0 - A8h
B0 - B8h
-
-
KON
C0 - C8h CHD
CHC
CHB
E0 - F5h
-
-
-
D4
D3
D2
D1
D0
LSI TEST
CONNECTION SEL
-
-
NEW3 NEW2 NEW
KSR
MULT
TL
DR
RR
F-NUM (L)
BLOCK
F-NUM (H)
CHA
FB
CNT
-
-
WS
Default :
After initial clear, all the bits of Register Array 1 are cleared to "0" except NEW2 and NEW3 bits of
index 05h, and CHA and CHB bits of index C0-C8h.
For the details of these registers, refer to data sheet for YMF289B(OPL3-L).
Note :
Since NEW2 and 3 (at index 05h of Register array1) = 1 in default state, both LD and BUSY0 bits
are valid. (LD and BUSY0 bits are invalid when NEW2=0.) BUSY0 is a BUSY flag for both FM
and Wavetable registers.
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July 10, 1997