YMF721 Datasheet, PDF (17/41 Pages) LSI Computer Systems – FM + Wavetable Synthesizer LSI

YMF721
6-4. Control/Status register
I/O port for Control/Status register is described here.
Control/Status Port (R/W):
port
D7
D6
D5
D4
D3
D2
D1
D0
OPL_Base + 7(W)
OPL_Base + 7(R)
PDY
PDY
PDX
PDX
-
-
-
MPR
“0”
“1”
-
BSEL
-
RESP GBUSY GDRQ
PDY, PDX...
MPR...
BSEL...
RESP...
GBUSY...
GDRQ...
Default : (00x1 x000)_b0
YMF721 recovers from power down mode by using the
following sequence.
PDY=“1”, PDX=“0”
¯ wait time (in case of using crystal oscillation)
PDY=“0”, PDX=“0”
D7 and D6 bits of Status register become "1" during power
down mode. In this state, oscillation of clock can be confirmed
by monitoring the status bit during power down mode in/out
sequence.
Setting this bit to "0" initializes internal processor. Default
value of this bit is "1".
This bit shows connection of internal bus of YMF721(OPL4-
ML2). Default value of this bit is "1".
“1” : Connecting synthesizer and internal processor
“0” : Connecting synthesizer and ISA bus
Indicates that a response to a command has been received.
Flag bit that indicates if data can be written into Command write
register.
“1” : BUSY
“0” : Data can be written
Flag bit that indicates if data can be read from Response
register.
“1” : READY
“0” : Reading is inhibited
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July 10, 1997