YMF721 Datasheet, PDF (18/41 Pages) LSI Computer Systems – FM + Wavetable Synthesizer LSI

YMF721
6-5. FM synthesizer registers
6-5-1. Status register
Status Register (RO):
port
D7
D6
D5
D4
D3
D2
D1
D0
OPL_Base + 0 IRQ
FT1
FT2
-
-
-
LD BUSY0
Note :
Since NEW2 (index 05h of Register array1) = 1 in default state, both LD and BUSY0 bits are valid.
(LD and BUSY0 bits are invalid when NEW2=0.) BUSY0 is a BUSY flag for both FM and
Wavetable registers.
6-5-2. Data register
Data Register Array 0 (R/W):
Index
D7
D6
D5
00 - 01h
02h
03h
04h
RST
MT1
MT2
08h
-
20 - 35h AM
NTS
VIB
-
EGT
40 - 55h
60 - 75h
KSL
AR
80 - 95h
A0 - A8h
B0 - B8h
BDh
C0 - C8h
-
DAM
CHD
SL
-
DVB
CHC
KON
RHY
CHB
E0 - F5h
-
-
-
D4
D3
D2
D1
D0
LSI TEST
TIMER 1
TIMER 2
-
-
-
ST2
ST1
-
-
-
-
-
KSR
MULT
TL
DR
RR
F-NUM (L)
BLOCK
F-NUM (H)
BD
SD
TOM
TC
HH
CHA
FB
CNT
-
-
WS
- 18 -
July 10, 1997