AMIS-30624 Datasheet, PDF (38/56 Pages) AMI SEMICONDUCTOR – I2C Microstepping Motordriver

AMIS-30624
2) If the microcontroller wants to receive information from motordriver_2:
• Microcontroller (master) addresses motordriver_2 (slave)
• Microcontroller (master-receiver) receives data from motordriver_2 (slave-transmitter)
• Microcontroller terminates the transfer
Even in this case the master generates the timing and terminates the transfer.
Generation of the signals on the I²C-bus is always the responsibility of the master device. It generates its own clock signal when
transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow slave device
holding-down the clock line.
15.3 General Characteristics
Serial Data Line
Serial Clock Line
SCK
2
Clock IN
Data IN
SDA
1
Clock OUT
Data OUT
AMIS-30624
SCL
SDA
Clock IN
Clock OUT
MASTER
Data IN
Data OUT
Figure 24: Connection of a Device to the I²C-bus
+5 V
R_p
R_p
PC20060925.7
Both SDA and SCK are bi-directional lines connected to a positive supply voltage via a pull-up resistor (see Figure 24). When the bus is
free both lines are HIGH. The output stages of the devices connected to the bus must have an open drain to perform the wired-AND
function. Data on the I²C-bus can be transferred up to 400kbits/s in fast mode. The number of interfaces connected to the bus is
dependent on the maximum bus capacitance limit (See C_B in Table 6) and the available number of addresses.
15.4 Bit Transfer
The levels for logic ‘0’ (LOW) and ‘1’ (HIGH) are not fixed in the I²C standard but dependent on the used VDD level. Using AMIS-30624,
the levels are specified in Table 5. One clock pulse is generated for each data bit transferred.
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