LTC3863 Datasheet, PDF (8/36 Pages) Linear Technology – 60V Low IQ Inverting DC/DC Controller Wide Operating VIN Range: 3.5V to 60V

LTC3863
PIN FUNCTIONS
PLLIN/MODE (Pin 1): External Reference Clock Input
and Burst Mode Enable/Disable. When an external clock
is applied to this pin, the internal phase-locked loop will
synchronize the turn-on edge of the gate drive signal with
the rising edge of the external clock. When no external
clock is applied, this input determines the operation during
light loading. Floating this pin selects low I_Q (40μA) Burst
Mode operation. Pulling to ground selects pulse-skipping
mode operation.
FREQ (Pin 2): Switching Frequency Setpoint Input. The
switching frequency is programmed by an external set-
point resistor R_FREQ connected between the FREQ pin and
signal ground. An internal 20µA current source creates
a voltage across the external setpoint resistor to set the
internal oscillator frequency. Alternatively, this pin can
be driven directly by a DC voltage to set the oscillator
frequency. Grounding selects a fixed operating frequency
of 350kHz. Floating selects a fixed operating frequency
of 535kHz.
SGND (Pin 3): Ground Reference for Small-Signal Analog
Component (Signal Ground). Signal ground should be
used as the common ground for all small-signal analog
inputs and compensation components. Connect the signal
ground to the power ground (ground reference for power
components) only at one point using a single PCB trace.
SS (Pin 4): Soft-Start and External Tracking Input. The
LTC3863 regulates the feedback voltage to the smaller of
0.8V or the voltage on the SS pin. An internal 10μA pull-up
current source is connected to this pin. A capacitor to
ground at this pin sets the ramp time to the final regulated
output voltage. Alternatively, another voltage supply con-
nected through a resistor divider to this pin allows the
output to track the other supply during start-up.
V_FB (Pin 5): Output Feedback Sense. A resistor divider
from the regulated output point to this pin sets the output
voltage. The LTC3863 will nominally regulate V_FB to the
internal reference value of 0.8V. If V_FB is less than 0.4V, the
switching frequency will linearly decrease and fold back
to about one-fifth of the internal oscillator frequency to
reduce the minimum duty cycle.
ITH (Pin 6): Current Control Threshold and Controller
Compensation Point. This pin is the output of the error
amplifier and the switching regulator’s compensation
point. The voltage ranges from 0V to 2.9V, with 0.8V cor-
responding to zero sense voltage (zero current).
V_FBN (Pin 7): Feedback Input for an Inverting PWM Con-
troller. Connect V_FBN to the center of a resistor divider
between the output and V_FB. The V_FBN threshold is 0V. To
defeat the inverting amplifier and use the LTC3863 as an
LTC3864 (noninverting buck), tie V_FBN > 2V.
RUN (Pin 8): Digital Run Control Input. A RUN voltage
above the 1.26V threshold enables normal operation, while
a voltage below the threshold shuts down the controller.
An internal 0.4µA current source pulls the RUN pin up to
about 3.3V. The RUN pin can be connected to an external
power supply up to 60V.
CAP (Pin 9): Gate Driver (–) Supply. A low ESR ceramic
bypass capacitor of at least 0.1µF or 10X the effective
C_MILLER of the P-channel power MOSFET, is required
from V_IN to this pin to serve as a bypass capacitor for the
internal regulator. To ensure stable low noise operation, the
bypass capacitor should be placed adjacent to the V_IN and
CAP pins and connected using the same PCB metal layer.
SENSE (Pin 10): Current Sense Input. A sense resistor,
R_SENSE, from the V_IN pin to the SENSE pin sets the maxi-
mum current limit. The peak inductor current limit is equal
to 95mV/R_SENSE. For accuracy, it is important that the V_IN
pin and the SENSE pin route directly to the current sense
resistor and make a Kelvin (4-wire) connection.
V_IN (Pin 11): Chip Power Supply. A minimum bypass
capacitor of 0.1µF is required from the V_IN pin to power
ground. For best performance use a low ESR ceramic
capacitor placed near the V_IN pin.
GATE (Pin 12): Gate Drive Output for External P-Channel
MOSFET. The gate driver bias supply voltage (V_IN-V_CAP)
is regulated to 8V when V_IN is greater than 8V. The gate
driver is disabled when (V_IN-V_CAP) is less than 3.5V (typi-
cal), 3.8V maximum in start-up and 3.25V (typical) 3.5V
maximum in normal operation.
PGND (Exposed Pad Pin 13): Ground Reference for Power
Components (Power Ground). The PGND exposed pad must
be soldered to the circuit board for electrical contact and
for rated thermal performance of the package. Connect
signal ground to power ground only at one point using a
single PCB trace.
3863f
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