LTC3863 Datasheet, PDF (26/36 Pages) Linear Technology – 60V Low IQ Inverting DC/DC Controller Wide Operating VIN Range: 3.5V to 60V

LTC3863
APPLICATIONS INFORMATION
C_INB
C_SS
C_PITH
C_{ITH RITH}
R_FREQ
GROUND
PLANE
TO PGND
C_CAP
RUN ^CAP V_IN
PLLIN/MODE
SS
SENSE
GATE
LTC3863
ITH
FREQ
SGND
V_FBN
PGND ^VFB
C_SF
R_SF
R_GATE
V_IN
C_IN
+
–^RSENSE
Q1 ^D1
L1
V_OUT
C_OUT
R_FB1
C_FB2 R_FB2
3863 F08
Figure 8: LTC3863 Generic Application Schematic with Optional
Current Sense Filter and Series Gate Resistor
C_INB
GATE
V_IN
SENSE
R_GATE
C_SF
C_CAP
TO Q1 GATE
TO R_SENSE+
CAP
R_SF
TO R_SENSE–
3863 F09
Figure 9: LTC3863 Recommended Gate Driver PC Board
Placement, Layout and Routing
C_CAP should be placed near the V_IN and CAP pins. Figure 9
shows C_CAP placed adjacent to the V_IN and CAP pins with
SENSE routed between the pads. This is the recommended
layout and results in the minimum parasitic inductance.
The gate driver is capable of providing high peak current.
Parasitic inductance in the gate drive and the series in-
ductance between V_IN to CAP can cause a voltage spike
between V_IN and CAP on each switching cycle. The voltage
spike can result in electrical over-stress to the gate driver
and can result in gate driver failures in extreme cases. It
is recommended to follow the example shown in Figure 9
for the placement of C_CAP as close as is practical.
R_GATE resistor pads can be added with a 0Ω resistor to
allow the damping resistor to be added later. The total
length of the gate drive trace to the PMOS gate should
be minimized and ideally be less than 1cm. In most cases
with a good layout the R_GATE resistor is not needed. The
R_GATE resistor should be located near the gate pin to re-
duce peak current through GATE and minimize reflected
noise on the gate pin.
The R_SF and C_SF pads can be added with a zero ohm resis-
tor for R_SF and C_SF not populated. In most applications,
external filtering is not needed. The current sense filter
R_SF and C_SF can be added later if noise if demonstrated
to be a problem.
The bypass capacitor C_INB is used to locally filter the
V_IN supply. C_INB should be tied to the V_IN pin trace and
to the PGND exposed pad. The C_INB positive pad should
connect to R_SENSE positive though the V_IN pin trace. The
C_INB ground trace should connect to the PGND exposed
pad connection.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3863.
1. Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking pur-
poses. Use wide rails and/or entire planes for V_IN, V_OUT
and GND for good filtering and minimal copper loss. If
a ground layer is used, then it should be immediately
below (and/or above) the routing layer for the power
train components which consist of C_IN, sense resistor,
P-channel MOSFET, Schottky diode, inductor, and C_OUT.
Flood unused areas of all layers with copper for better
heat sinking.
2. Keep signal and power grounds separate except at the
point where they are shorted together. Short the signal
and power ground together only at a single point with a
narrow PCB trace (or single via in a multilayer board).
All power train components should be referenced to
power ground and all small-signal components (e.g.,
C_ITH1, R_FREQ, C_SS etc.) should be referenced to the
signal ground.
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