LTC3863 Datasheet, PDF (11/36 Pages) Linear Technology – 60V Low IQ Inverting DC/DC Controller Wide Operating VIN Range: 3.5V to 60V

LTC3863
OPERATION
The start-up of the output voltage V_OUT is controlled by
the voltage on the SS pin. When the voltage on the SS
pin is less than the 0.8V internal reference, the V_FB pin is
regulated to the voltage on the SS pin. This allows the SS
pin to be used to program a soft-start by connecting an
external capacitor from the SS pin to signal ground. An
internal 10µA pull-up current charges this capacitor, creat-
ing a voltage ramp on the SS pin. As the SS voltage rises
from 0V to 0.8V, the output voltage V_OUT rises smoothly
from zero to its final value.
Alternatively, the SS pin can be used to cause the start-up of
V_OUT to track that of another supply. Typically, this requires
connecting the SS pin to an external resistor divider from
the other supply to ground (see Applications Information).
Under shutdown or UVLO, the SS pin is pulled to ground
and prevented from ramping up.
If the slew rate of the SS pin is greater than 1.2V/ms, the
output will track an internal soft-start ramp instead of the
SS pin. The internal soft-start will guarantee a smooth
start-up of the output under all conditions, including in the
case of a short-circuit recovery where the output voltage
will recover from near ground.
Light Load Current Operation (Burst Mode Operation
or Pulse-Skipping Mode)
The LTC3863 can be enabled to enter high efficiency Burst
Mode operation or pulse-skipping mode at light loads. To
select pulse-skipping operation, tie the PLLIN/MODE pin
to signal ground. To select Burst Mode operation, float
the PLLIN/MODE pin.
In Burst Mode operation, if the V_FB is higher than the refer-
ence voltage, the error amplifier will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high, enabling sleep mode.
The ITH pin is then disconnected from the output of the
error amplifier and held at 0.45V.
In sleep mode, much of the internal circuitry is turned
off, reducing the quiescent current to 70µA while the
load current is supplied by the output capacitor. As the
output voltage and hence the feedback voltage decreases,
the error amplifier’s output will rise. When the output
voltage drops enough, the ITH pin is reconnected to the
output of the error amplifier, the sleep signal goes low,
and the controller resumes normal operation by turning
on the external P-channel MOSFET on the next cycle of
the internal oscillator. In Burst Mode operation, the peak
inductor current has to reach at least 25% of current
limit for the current comparator, ICMP, to trip and turn the
P-channel MOSFET back off, even though the ITH voltage
may indicate a lower current setpoint value.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3863 will skip pulses during light loads. In
this mode, ICMP may remain tripped for several cycles and
force the external MOSFET to stay off, thereby skipping
pulses. This mode offers the benefits of smaller output
ripple, lower audible noise, and reduced RF interference,
at the expense of lower efficiency when compared to Burst
Mode operation.
Frequency Selection and Clock Synchronization
The switching frequency of the LTC3863 can be selected
using the FREQ pin. If the PLLIN/MODE pin is not being
driven by an external clock source, the FREQ pin can be
tied to signal ground, floated, or programmed through
an external resistor. Tying FREQ to signal ground selects
350kHz, while floating selects 535kHz. Placing a resistor
between FREQ and signal ground allows the frequency to
be programmed between 50kHz and 850kHz.
The phase-locked loop (PLL) on the LTC3863 will syn-
chronize the internal oscillator to an external clock source
when connected to the PLLIN/MODE pin. The PLL forces
the turn-on edge of the external P-channel MOSFET to be
aligned with the rising edge of the synchronizing signal.
For more information www.linear.com/3863
3863f
11