LTC3863 Datasheet, PDF (25/36 Pages) Linear Technology – 60V Low IQ Inverting DC/DC Controller Wide Operating VIN Range: 3.5V to 60V

LTC3863
APPLICATIONS INFORMATION
V_R = 80V, θ_JA = 55°C/W) for this application. The power
dissipation and junction temperature at T_A = 70° and full
load = 1.8A can be calculated as:
P_DIODE = 1.8A • 0.45V = 0.81W
T_J = 70°C + 0.81W • 55°C/W = 114°C
These power dissipation calculations show that careful
attention to heat sinking will be necessary.
For the input bypass capacitors, choose low ESR ceramic
capacitors that can handle the maximum RMS current at
the minimum V_IN of 4.5V:
I_CIN(RMS) ≈ 1.8A •
| –5V| _{= 1.9A}
4.5V
C_OUT will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement. For this
design, two 47μF ceramic capacitors are chosen to offer
low ripple in both normal operation and in Burst Mode
operation.
The selected C_OUT must support the maximum RMS
operating current at a minimum V_IN of 4.5V:
I_CIN(RMS) ≈ 1.8A •
| –5V|
4.5V
=
1.9A
A soft-start time of 8ms can be programmed through a
0.1μF capacitor on the SS pin:
C_SS
=
8ms •10µA
0.8V
=
0.1µF
Loop compensation components on the ITH pin are chosen
based on load step transient behavior (as described under
OPTI-LOOP Compensation) and is optimized for stability. A
pull-up resistor is used on the RUN pin for FMEA compli-
ance (see Failure Modes and Effects Analysis).
An application with complementary dual outputs of ±5V
can be designed by using two LTC3863 parts with one
configured into an inverting regulator and the other into
a step-down buck regulator as shown in Figure 11. Refer
to LTC3864 data sheet for the actual design of a buck
output of 5V.
Gate Driver Component Placement,
Layout and Routing
It is important to follow recommended power supply PC
board layout practices such as placing external power ele-
ments to minimize loop area and inductance in switching
paths. Be careful to pay particular attention to gate driver
component placement, layout and routing.
The effective C_CAP capacitance should be greater than 0.1µF
minimum in all operating conditions. Operating voltage
and temperature both decrease the rated capacitance to
varying degrees depending on dielectric type. The LTC3863
is a PMOS controller with an internal gate driver and boot-
strapped LDO that regulates the differential CAP voltage
(V_IN – V_CAP) to 8V nominal. The C_CAP capacitance needs
to be large enough to assure stability and provide cycle-
to-cycle current to the PMOS switch with minimum series
inductance. We recommend a ceramic 0.47µF 16V capacitor
with a high quality dielectric such as X5R or X7R. Some
high current applications with large Qg PMOS switches
may benefit from an even larger C_CAP capacitance.
Figure 8 shows the LTC3863 Generic Application Sche-
matic which includes an optional current sense filter and
series gate resistor. Figure 9 illustrates the recommended
gate driver component placement, layout and routing of
the GATE, V_IN, SENSE and CAP pins and key gate driver
components. It is recommended that the gate driver layout
follow the example shown in Figure 9 to assure proper
operation and long term reliability.
The LTC3863 gate driver should connect to the external
power elements in the following manner. First route the
V_IN pin using a single low impedance isolated trace to
the positive R_SENSE resistor PAD without connection to
the V_IN plane. The reason for this precaution is that the
V_IN pin is internally Kelvin connected to the current sense
comparator, internal V_IN power and the PMOS gate driver.
Connecting the V_IN pin to the V_IN power plane adds noise
and can result in jitter or instability. Figure 9 shows a single
V_IN trace from the positive R_SENSE pad connected to C_SF,
C_CAP, V_IN pad and C_INB. The total trace length to R_SENSE
should be minimized and the capacitors C_CF, C_CAP and
C_INB should be placed near the V_IN pin of the LTC3863.
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