LTC3834-1 Datasheet, PDF (8/28 Pages) Linear Technology – 30μA IQ Synchronous Step-Down Controller

LTC3834-1
PI FU CTIO S (DHC Package/GN Package)
ler functions, reducing the quiescent current that the
LTC3834-1 draws to approximately 4μA.
SENSE^– (Pin 14/Pin 14): The (–) Input to the Differential
Current Comparator.
SENSE⁺ (Pin 15/Pin 15): The (+) Input to the Differential
Current Comparator. The I_TH pin voltage and controlled
offsets between the SENSE^– and SENSE⁺ pins in conjunc-
tion with R_SENSE set the current trip threshold.
PLLIN/MODE (Pin 16/Pin 16): External Synchronization
Input to Phase Detector and Forced Continuous Control
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG signal to be
synchronized with the rising edge of the external clock. In
this case, an R-C filter must be connected to the PLLLPF
pin. When not synchronizing to an external clock, this
input determines how the LTC3834-1 operates at light
loads. Pulling this pin below 0.7V selects Burst Mode
operation. Tying this pin to INTV_CC forces continuous
inductor current operation. Tying this pin to a voltage
greater than 0.9V and less than INTV_CC selects pulse-
skipping operation.
Exposed Pad (Pin 17, DHC Package): SGND. Must be
soldered to PCB.
W
FU CTIO AL DIAGRA
PLLIN/MODE
F_IN
PHASE DET
R_LP ^PLLLPF
CLK
OSCILLATOR
C_LP
INTV_CC-0.5V
–
+
PLLIN/MODE
–
0.8V +
FC
BURSTEN
INTV_CC
V_IN
BOOST
D_B
DROP
OUT
DET
SQ
BOT FC
TOP ON
TG
TOP
SW
RQ
SWITCH
LOGIC
INTV_CC
BG
BOT
BURSTEN
0.4V + ^B
SLEEP
–
SHDN
PGND
C_B
D
C_IN
C_OUT
V_OUT
L
R_SENSE
8
V_IN
V_IN
INTV_CC
+
SGND
LDO
5.25V
INTERNAL
SUPPLY
ICMP
–
0.45V
2(V_FB)
SLOPE
COMP
0.5μA
IR
–
++ –
+
6mV
EA
OV
V_FB
TRACK/SS
0.80V
0.88V
SENSE⁺
SENSE^–
V_FB
I_TH
6V
RUN
1μA
TRACK/SS
SHDN
R_B
R_A
C_C
C_C2
R_C
C_SS
3834-1 FD
38341f