LTC3834-1 Datasheet, PDF (11/28 Pages) Linear Technology – 30μA IQ Synchronous Step-Down Controller

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OPERATIO (Refer to Functional Diagram)
The typical capture range of the LTC3834-1’s phase-
locked loop is from approximately 115kHz to 800kHz,
with a guarantee to be between 140kHz and 650kHz. In
other words, the LTC3834-1’s PLL is guaranteed to lock to
an external clock source whose frequency is between
140kHz and 650kHz.
The typical input clock thresholds on the PLLIN/MODE pin
are 1.6V (rising) and 1.2V (falling).
LTC3834-1
Output Overvoltage Protection
An overvoltage comparator guards against transient over-
shoots as well as other more serious conditions that
may overvoltage the output. When the V_FB pin rises to
more than 10% higher than its regulation point of
0.800V, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition
is cleared.
APPLICATIO S I FOR ATIO
R_SENSE Selection for Output Current
R_SENSE is chosen based on the required output current.
The current comparator has a maximum threshold of
100mV/R_SENSE and an input common mode range of
SGND to 10V. The current comparator threshold sets the
peak of the inductor current, yielding a maximum average
output current I_MAX equal to the peak value less half the
peak-to-peak ripple current, I _L.
Allowing a margin for variations in the IC and external
component values yields:
R_SENSE
=
80mV
I_MAX
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet stability crite-
rion for buck regulators operating at greater than 50%
duty factor. A curve is provided to estimate this reduction
in peak output current level depending upon the operating
duty factor.
Operating Frequency and Synchronization
The choice of operating frequency, is a trade-off between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses,
both gate charge loss and transition loss. However, lower
frequency operation requires more inductance for a given
amount of ripple current.
The internal oscillator of the LTC3834-1 runs at a nominal
400kHz frequency when the PLLLPF pin is left floating and
the PLLIN/MODE pin is a DC low or high. Pulling the
PLLLPF to INTV_CC selects 530kHz operation; pulling the
PLLLPF to SGND selects 250kHz operation.
Alternatively, the LTC3834-1 will phase-lock to a clock
signal applied to the PLLIN/MODE pin with a frequency
between 140kHz and 650kHz (see Phase-Locked Loop
and Frequency Synchronization).
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current I _L decreases with higher
inductance or frequency and increases with higher V_IN:
ΔI_L
=
1
(f)(L)
⎛
V_{OUT ⎝⎜} 1–
V_OUT
V_IN
⎞
⎠⎟
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