LTC3834-1 Datasheet, PDF (22/28 Pages) Linear Technology – 30μA IQ Synchronous Step-Down Controller

LTC3834-1
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. These items are also illustrated graphically in the
layout diagram of Figure 8. The Figure 9 illustrates the
current waveforms present in the various branches of the
synchronous regulator operating in the continuous mode.
Check the following in your layout:
1. Is the top N-channel MOSFET M1 located within 1cm
of C_IN?
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C_INTVCC must return to the combined C_OUT (–) termi-
nals. The path formed by the top N-channel MOSFET,
Schottky diode and the C_IN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible to
the (–) terminals of the input capacitor by placing the
capacitors next to each other and away from the Schottky
loop described above.
3. Does the LTC3834-1 V_FB pin resistive divider connect to
the (+) terminals of C_OUT? The resistive divider must be
connected between the (+) terminal of C_OUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
4. Are the SENSE ^– and SENSE ⁺ leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE ⁺ and SENSE ^– should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the SENSE resistor.
5. Is the INTV_CC decoupling capacitor connected close to
the IC, between the INTV_CC and the power ground pins?
This capacitor carries the MOSFET drivers current
peaks. An additional 1μF ceramic capacitor placed
immediately next to the INTV_CC and PGND pins can help
improve noise performance substantially.
6. Keep the switching node (SW), top gate node (TG), and
boost node (BOOST) away from sensitive small-signal
nodes, especially from the opposites channel’s voltage
and current sensing feedback pins. All of these nodes
have very large and fast moving signals and therefore
should be kept on the “output side” of the LTC3834-1
and occupy minimum PC trace area.
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV_CC
decoupling capacitor, the bottom of the voltage feed-
back resistive divider and the SGND pin of the IC.
22
TRACK/SS
SENSE⁺
TG
SENSE^–
SW
LTC3834EGN-1
V_FB
BOOST
PLLLPF
V_IN
f_IN
PLLIN/MODE
BG
RUN
I_TH
SGND
INTV_CC
PGND
L1
R_SENSE
V_OUT
C_B
M1
M2
D1
Optional
D_B
C_INTVCC
R_IN
C_VIN
V_IN
1μF
CERAMIC
C_IN
3834-1 F08
C_OUT
GND
Figure 8. LTC3834-1 Recommended Printed Circuit Layout Diagram
38341f