LTC3831-1 Datasheet, PDF (8/20 Pages) Linear Technology – High Power Synchronous Switching Regulator Controller for DDR Memory Termination

LTC3831-1
TEST CIRCUITS
NC
NC
V_FB
V_COMP
1.5V
PV_CC
V_SHDN V_CC
+
SHDN
SS
FREQSET
FB
COMP
R⁺
R^–
V_CC PV_CC2 PV_CC1 I_FB
TG
LTC3831-1
I_MAX
GND
BG
PGND
10µF
0.1µF
TG RISE/FALL
6800pF
BG RISE/FALL
6800pF
38311 F01
Figure 1
APPLICATIO S I FOR ATIO
OVERVIEW
The LTC3831-1 is a voltage mode feedback, synchronous
switching regulator controller (see Block Diagram) de-
signed for use in high to medium power, DDR memory
termination. It includes an onboard PWM generator, a
ratiometric reference, two high power MOSFET gate driv-
ers and all necessary feedback and control circuitry to
form a complete switching regulator circuit. The PWM
loop nominally runs at 300kHz.
The LTC3831-1 is designed to generate an output voltage
that tracks at 1/2 of the external voltage connected between
the R⁺ and R^– pins. The LTC3831-1 can be used to gener-
ate the termination voltage, V_TT, for interface like the SSTL_2
where V_TT is a ratio of the interface supply voltage, V_DDQ.
It is a requirement in the SSTL_2 interface standard for V_TT
to track the interface supply voltage to improve noise im-
munity. Using the LTC3831-1 to supply the interface ter-
mination voltage allows large current sourcing and sink-
ing through the termination resistors during bus transitions.
The LTC3831-1 includes a current limit sensing circuit that
uses the topside external N-channel power MOSFET as a
current sensing element, eliminating the need for an
external sense resistor. Also included is an internal soft-
start feature that requires only a single external capacitor
to operate. In addition, the part features an adjustable
oscillator which can free run or synchronize to an external
signal with frequencies from 100kHz to 500kHz, allowing
added flexibility in external component selection.
8
THEORY OF OPERATION
Primary Feedback Loop
The LTC3831-1 senses the output voltage of the circuit
through the FB pin and feeds this voltage back to the
internal transconductance error amplifier, ERR. The error
amplifier compares the output voltage to the internal
ratiometric reference, V_REF, and outputs an error signal to
the PWM comparator. V_REF is set to 0.5 multiplied by the
voltage difference between the R⁺ and R^– pins, using an
internal resistor divider.
This error signal is compared with a fixed frequency ramp
waveform, from the internal oscillator, to generate a pulse
width modulated signal. This PWM signal drives the
external MOSFETs through the TG and BG pins. The
resulting chopped waveform is filtered by L_O and C_OUT
which closes the loop. Loop compensation is achieved
with an external compensation network at the COMP pin,
the output node of the error amplifier.
MAX Feedback Loop
An additional comparator in the feedback loop provides
high speed output voltage correction in situations where
the error amplifier may not respond quickly enough. MAX
compares the feedback signal to a voltage 10% above
V_REF. If the signal is above the comparator threshold, the
MAX comparator overrides the error amplifier and forces
the loop to minimum duty cycle, 0%. To prevent this
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