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| LTC3831-1 Datasheet, PDF (13/20 Pages) Linear Technology – High Power Synchronous Switching Regulator Controller for DDR Memory Termination | |||
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LTC3831-1
APPLICATIO S I FOR ATIO
VDDQ
1.5V
12V
3.3V
2.2µF
C1
33pF
4.7µF
0.01µF
PVCC2 PVCC1
VCC
TG
SS
IMAX
LTC3831-1 IFB
FREQSET
BG
SHDN
SHDN
PGND
RC
1k
CC
10nF
COMP
GND
R+
Râ
FB
10k
0.1µF
Q1
1k
Q2
CIN: SANYO POSCAP 4TPB220M
COUT: SANYO POSCAP 4TPB470M
Q1, Q2: SILICONIX Si4410DY
+ CIN
220µF
MBRS340T3
LO
1.2µH
MBRS340T3
+
COUT
470µF
VTT
(VOUT)
0.9V
± 6A
2k
1%
10k
1%
38311 F06
Figure 6. Typical Application with VTT = 0.6 ⢠VDDQ
Power MOSFETs
Two N-channel power MOSFETs are required for most
LTC3831-1 circuits. These should be selected based pri-
marily on threshold voltage and on-resistance consider-
ations. Thermal dissipation is often a secondary concern
in high efficiency designs. The required MOSFET thresh-
old should be determined based on the available power
supply voltages and/or the complexity of the gate drive
charge pump scheme. In 3.3V input designs where an
auxiliary 12V supply is available to power PVCC1 and PVCC2,
standard MOSFETs with RDS(ON) specified at VGS = 5V or
6V can be used with good results. The current drawn from
this supply varies with the MOSFETs used and the LTC3831-
1âs operating frequency, but is generally less than 50mA.
LTC3831-1 applications that use 5V or lower VIN voltage
and tripling charge pumps to generate PVCC1 and PVCC2,
do not provide enough gate drive voltage to fully enhance
standard power MOSFETs. Under this condition, the effec-
tive MOSFET RDS(ON) may be quite high, raising the
dissipation in the FETs and reducing efficiency. Logic-
level or sub-logic level FETs are the recommended choice
for 5V or lower voltage systems. Logic-level FETs can be
fully enhanced with a tripling charge pump and will oper-
ate at maximum efficiency.
After the MOSFET threshold voltage is selected, choose
the RDS(ON) based on the input voltage, the output voltage,
allowable power dissipation and maximum output cur-
rent. In a typical LTC3831-1 circuit operating in continu-
ous mode, the average inductor current is equal to the
output load current. This current flows through either Q1
or Q2 with the power dissipation split up according to the
duty cycle:
DC(Q1) = VOUT
VIN
DC(Q2) = 1â VOUT = VIN â VOUT
VIN
VIN
The RDS(ON) required for a given conduction loss can now
be calculated by rearranging the relation P = I2R.
RDS(ON)Q1 =
PMAX(Q1)
DC(Q1) ⢠(ILOAD)2
=
VIN ⢠PMAX(Q1)
VOUT ⢠(ILOAD)2
RDS(ON)Q2
=
PMAX(Q2)
DC(Q2) ⢠(ILOAD)2
=
VIN ⢠PMAX(Q2)
(VIN â VOUT) ⢠(ILOAD)2
PMAX should be calculated based primarily on required
efficiency or allowable thermal dissipation. A typical high
38311f
13
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