LTC3831-1 Datasheet, PDF (17/20 Pages) Linear Technology – High Power Synchronous Switching Regulator Controller for DDR Memory Termination

LTC3831-1
APPLICATIO S I FOR ATIO
Table 2 shows the suggested compensation component
value for 1.5V to 0.75V applications based on the 470µF
Sanyo POSCAP 4TPB470M output capacitors.
Table 3 shows the suggested compensation component
values for 1.5V to 0.75V applications based on 1500µF
Sanyo MV-WX output capacitors.
LAYOUT CONSIDERATIONS
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3831-1. These items are also illustrated graphically in
the layout diagram of Figure 8. The thicker lines show the
high current paths. Note that at 5A current levels or above,
current density in the PC board itself is a serious concern.
Table 2. Recommended Compensation Network for 1.5V to
0.75V Applications Using Multiple Paralleled 470µF Sanyo
POSCAP 4TPB470M Output Capacitors
L1 (µH)
1.2
C_OUT (µF)
1410
R_C (kΩ)
5.6
C_C (nF)
3.3
C1 (pF)
68
1.2
2820
12
3.3
33
1.2
4700
20
2.2
22
2.4
1410
12
3.3
33
2.4
2820
27
1.5
15
2.4
4700
43
1.0
10
4.7
1410
24
1.5
15
4.7
2820
51
1.0
10
4.7
4700
93
3.3
10
Table 3. Recommended Compensation Network for 1.5V to
0.75V Applications Using Multiple Paralleled 1500µF Sanyo
MV-WX Output Capacitors
L1 (µH)
1.2
C_OUT (µF)
4500
R_C (kΩ)
15
C_C (nF)
2.2
C1 (pF)
120
1.2
6000
18
2.2
82
1.2
9000
30
1
56
2.4
4500
30
1
56
2.4
6000
39
1
33
2.4
9000
62
1
27
4.7
4500
62
1
27
4.7
6000
82
1
22
4.7
9000
130
1
10
V_CC
PV_CC
V_IN/V_DDQ
C1
R_C
C_C
2.2µF
NC
V_CC
PV_CC2
PV_CC1
TG
LTC3831-1
I_MAX
FREQSET
I_FB
SHDN
R⁺
COMP
BG
SS
FB
R^–
GND PGND
C_SS
GND
4.7µF 10k
PGND
0.1µF
1k
+
C_IN
OPTIONAL
Q1
MBRS340T3
L_O
MBRS340T3
Q2
PGND
Figure 8. Typical Schematic Showing Layout Considerations
V_OUT
+
C_OUT
38311 F08
38311f
17