LTC3831-1 Datasheet, PDF (10/20 Pages) Linear Technology – High Power Synchronous Switching Regulator Controller for DDR Memory Termination

LTC3831-1
APPLICATIO S I FOR ATIO
actual current limit to be greater than the desired current
limit set point. Due to switching noise and variation of
R_DS(ON), the actual current limit trip point is not highly
accurate. The current limiting circuitry is primarily meant
to prevent damage to the power supply circuitry during
fault conditions. The exact current level where the limiting
circuit begins to take effect will vary from unit to unit as the
R_DS(ON) of Q1 varies. Typically, R_DS(ON) varies as much as
±40% and with ±25% variation on the LTC3831-1’s I_MAX
current, this can give a ±65% variation on the current limit
threshold.
The R_DS(ON) is high if the V_GS applied to the MOSFET is
low. This occurs during power up, when PV_CC1 is ramping
up. To prevent the high R_DS(ON) from activating the current
limit, the LTC3831-1 disables the current limit circuit if
PV_CC1 is less than 2V above V_CC. To ensure proper
operation of the current limit circuit, PV_CC1 must be at
least 2V above V_CC when TG is high. PV_CC1 can go low
when TG is low, allowing the use of an external charge
pump to power PV_CC1.
V_IN
LTC3831-1
+
CC
–
12µA
R_IMAX
0.1µF
12
I_MAX
I_FB
13
TG
1k
Q1
L_O
BG
Q2
+
C_IN
+
V_OUT
C_OUT
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Figure 2. Current Limit Setting
Oscillator Frequency
The LTC3831-1 includes an onboard current controlled
oscillator that typically free-runs at 300kHz. The oscillator
frequency can be adjusted by forcing current into or out of
the FREQSET pin. With the pin floating, the oscillator runs
at about 300kHz. Every additional 1µA of current into/out
of the FREQSET pin decreases/increases the frequency by
10kHz. The pin is internally servoed to 1.265V. The fre-
quency can be estimated as:
f = 300kHz + ^{1.265V – VEXT} • ^10kHz
R_FSET
1µA
10
where R_FSET is a frequency programming resistor con-
nected between FREQSET and the external voltage source
V_EXT. Connecting an 82k resistor from FREQSET to ground
forces 15µA out of the pin, causing the internal oscillator
to run at approximately 450kHz. Forcing an external 20µA
current into FREQSET cuts the internal frequency to 100kHz.
An internal clamp prevents the oscillator from running
slower than about 50kHz. Tying FREQSET to V_CC forces
the chip to run at this minimum speed.
Shutdown
The LTC3831-1 includes a low power shutdown mode,
controlled by the logic at the SHDN pin. A high at SHDN
allows the part to operate normally. A low level at SHDN for
more than 100µs forces the LTC3831-1 into shutdown
mode. In this mode, all internal switching stops, the COMP
and SS pins pull to ground and Q1 and Q2 turn off. The
LTC3831-1 supply current drops to <10µA, although off-
state leakage in the external MOSFETs may cause the total
V_IN current to be somewhat higher, especially at elevated
temperatures. If SHDN returns high, the LTC3831-1 re-
runs a soft-start cycle and resumes normal operation.
External Clock Synchronization
The LTC3831-1 SHDN pin doubles as an external clock
input for applications that require a synchronized clock.
An internal circuit forces the LTC3831-1 into external
synchronization mode if a negative transition at the SHDN
pin is detected. In this mode, every negative transition on
the SHDN pin resets the internal oscillator and pulls the
ramp signal low. This forces the LTC3831-1 internal
oscillator to lock to the external clock frequency.
The LTC3831-1 internal oscillator can be externally syn-
chronized from 100kHz to 500kHz. Frequencies above
300kHz can cause a decrease in the maximum obtainable
duty cycle as rise/fall time and propagation delay take up
a larger percentage of the switch cycle. The low period of
this clock signal must not be >100µs or else the LTC3831-1
enters into the shutdown mode.
Figure 3 describes the operation of the external synchro-
nization function. A negative transition at the SHDN pin
forces the internal ramp signal low to restart a new PWM
cycle. Notice that the ramp amplitude is lowered as the
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