LTC3831-1 Datasheet, PDF (11/20 Pages) Linear Technology – High Power Synchronous Switching Regulator Controller for DDR Memory Termination

LTC3831-1
APPLICATIO S I FOR ATIO
external clock frequency goes higher. The effect of this
decrease in ramp amplitude increases the open-loop gain
of the controller feedback loop. As a result, the loop
crossover frequency increases and it may cause the feed-
back loop to be unstable if the phase margin is insufficient.
To overcome this problem, the LTC3831-1 monitors the
peak voltage of the ramp signal and adjust the oscillator
charging current to maintain a constant ramp peak.
SHDN
200kHz
FREE RUNNING
RAMP SIGNAL
TRADITIONAL
SYNC METHOD
WITH EARLY
RAMP
TERMINATION
RAMP SIGNAL
WITH EXT SYNC
RAMP AMPLITUDE
ADJUSTED
LTC3831
KEEPS RAMP
AMPLITUDE
CONSTANT
UNDER SYNC
38311 F03
Figure 3. External Synchronization Operation
Input Supply Considerations/Charge Pump
The LTC3831-1 requires four supply voltages to operate:
V_IN for the main power input, PV_CC1 and PV_CC2 for MOS-
FET gate drive and a clean, low ripple V_CC for the LTC3831-1
internal circuitry (Figure 4). V_IN is usually connected to
V_DDQ in most DDR memory termination applications.
The V_CC supply can be as low as 3V and the quiescent
current is typically 800µA. Place a 4.7µA bypass capacitor
as close as possible to this pin. Gate drive for the top
N-channel MOSFET Q1 is supplied from PV_CC1. This
supply must be above V_IN by at least one power MOSFET
V_GS(ON) for efficient operation. In addition, this supply
must be higher that V_CC by at least 2V for normal opera-
tion. An internal level shifter allows PV_CC1 to operate at
voltages above V_CC and V_IN, up to 14V maximum. This
higher voltage can be supplied with a separate supply, or
it can be generated using a charge pump.
Gate drive for the bottom MOSFET Q2 is provided through
PV_CC2. This supply only needs to be above the power
MOSFET V_GS(ON) for efficient operation. PV_CC2 can also be
driven from the same supply/charge pump for the PV_CC1,
or it can be connected to a lower supply to improve
efficiency.
In a typical low voltage DDR memory termination applica-
tion, V_IN or V_DDQ can be a low as 1.5V. If the only available
supply for the LTC3831-1 is 3.3V, a tripling charge pump
circuit can be added to power the PV_CC1 and PV_CC2 pins.
This requires sub-logic level threshold power MOSFET
with R_DS(ON) specified at V_GS = 2.5V.
Figure 5 shows a tripling charge pump circuit that powers
the PV_CC1 and PV_CC2 pins. This circuit provides (V_CC +
2V_IN – 3V_F) to PV_CC1 while Q1 is ON and (V_CC + V_IN – 2V_F)
to PV_CC2 where V_F is the ON voltage of the Schottky diode.
The circuit requires the use of Schottky diodes to minimize
forward drop across the diodes at start-up. The tripling
charge pump circuit will tend to rectify any ringing at the
drain of Q2 and can provide well more than (V_CC + 2V_IN)
at PV_CC1. A 12V zener diode may be included from PV_CC1
to PGND to prevent transients from damaging the circuitry
at PV_CC1 or the gate of Q1.
V_CC
PV_CC2 PV_CC1
V_IN
INTERNAL
CIRCUITRY
LTC3831-1
TG
Q1
L_O
V_OUT
BG
Q2
+
C_OUT
38311 F04
Figure 4. Input Supplies
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