LTC3618_15 Datasheet, PDF (8/24 Pages) Linear Technology – Dual 4MHz, 3A Synchronous Buck Converter for DDR Termination

LTC3618
Pin Functions (FE/UF)
PHASE (Pin 1/Pin 4): Phase Shift Selection. If pin is tied
to SGND, the phase between SW1 and SW2 will be 0°.
Tying PHASE to SV_IN will select 180° phase shift. With
the PHASE pin tied to half of the SV_IN voltage, 90° phase
shift will be selected.
V_FB2 (Pin 2/Pin 5): Voltage Feedback Input Pin for V_TT.
See V_FB1.
ITH2 (Pin 3/Pin 6): Error Amplifier Compensation of V_TT.
See ITH1.
VDDQIN (Pin 4 /Pin 7): External Reference Input. An
internal resistor divider to the error amplifier sets the
output voltage of V_TT. V_FB2 will regulate to VDDQIN • 0.5.
SGND (Pin 5/Pin 8): Signal Ground. All small-signal and
compensation components should connect to this ground
pin which, in turn, should be connected to PGND at one
point.
PV_IN2 (Pins 6, 7/Pins 9, 10) V_TT Power Supply Input.
See PV_IN1.
SW2 (Pins 8, 9/Pins 11, 12): V_TT Switch Node. See SW1.
RUN2 (Pin 10/Pin 13): Enable Pin for V_TT. See RUN1.
RUN1 (Pin 11/Pin 14): Enable Pin for V_DDQ. Forcing RUN1
above the input threshold voltage enables the output SW1
of V_DDQ. Forcing both RUNx pins to ground shuts down
the LTC3618. In shutdown, all functions are disabled and
the LTC3618 draws <1µA of supply current.
RT (Pin 12/Pin 15): Oscillator Frequency. This pin provides
two modes of setting the switching frequency.
1. Connecting a resistor from RT to ground will set the
switching frequency based on the resistor value.
2. Tying this pin to SV_IN enables the internal 2.25MHz
oscillator frequency.
PGOOD2 (Pin 13/Pin 16): Power Good Output for
V_TT. See PGOOD1.
VTTR (Pin 14 /Pin 17): Voltage Buffer Output. This pin is
the output of an internal voltage buffer whose voltage is
equal to VDDQIN • 0.5. Output current capability is ±10mA.
Do not exceed 0.1µF capacitance on this pin. This output
is enabled/disabled by RUN2.
PGOOD1 (Pin 15/Pin 18): Power Good Output Pin for
V_DDQ. The open-drain output will be pulled down to ground
if the FB1 voltage of the channel is not within the power
good voltage window. The PGOOD1 will also be pulled
down if the channel is not enabled with the RUN1 pin or an
undervoltage at SV_IN is detected. The power good window
moves in relation to the actual TRACK/SS1 pin voltage.
SW1 (Pins 17, 16/Pins 19, 20): V_DDQ Switch Node.
Connection to the external inductor. This pin connects
to the drains of the internal synchronous power MOSFET
switches.
PV_IN1 (Pins 18, 19/Pins 21, 22): V_DDQ Power Supply
Inputs. These pins connect to the source of the internal
power P-channel MOSFET of V_DDQ. P_VIN1 and P_VIN2 are
independent of each other. They may connect to equal or
lower supplies than S_VIN.
SV_IN (Pin 20/Pin 23) Signal Input Supply. This pin pow-
ers the internal control circuitry and is monitored by the
undervoltage lockout comparator.
TRACK/SS1 (Pin 21/Pin 24): Internal, External Soft-Start,
External Reference Input for V_DDQ. The type of start-up be-
havior for V_DDQ is programmable with the TRACK/SS1 pin:
1. Internal soft-start with fixed timing can be programmed
by tying TRACK/SS1 to SV_IN.
2. External soft-start can be programmed with the timing
set by a capacitor to ground and a resistor to SV_IN.
3. Tracking the start-up behavior of another supply is
programmable (see the Applications Information
section).
4. The pin can be used as external reference input.
ITH1 (Pin 23/Pin 2): Error Amplifier Compensation. Con-
nection for external compensation from ITH to SGND.
The current comparator’s threshold increases with this
control voltage. Tying this pin to SV_IN enables internal
compensation.
V_FB1 (Pin 22/Pin 1): Voltage Feedback Input Pin for
V_DDQ. Receives the feedback voltage for V_DDQ from the
external resistive divider across the output.
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