LTC3618_15 Datasheet, PDF (19/24 Pages) Linear Technology – Dual 4MHz, 3A Synchronous Buck Converter for DDR Termination

LTC3618
Applications Information
Next, calculate the inductor values for approximately 1A
ripple current at maximum V_IN:
L1=
1.8V
2.25MHz • 1A
•
1– ^1.8V
5.5V
= 0.54µH
L2 = ^0.9V
• 1– ^0.9V
2.25MHz • 1A
5.5V
= _0.33µH
Using a standard value of 0.45µH inductor for both chan-
nels results in maximum ripple currents of:
I_L1 =
1.8V
• 1– ^1.8V = 1.2A
2.25MHz • 0.45µH
5.5V
I_L2 =
0.9V
• 1– ^0.9V
2.25MHz • 0.45µH
5.5V
= 0.71A
C_OUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, 47µF
ceramic capacitors will be used with X5R or X7R dielectric.
C_IN should be sized for a maximum current rating of:
I_{R M S(M AX )}
=
I_OUT1
2
+
I
OUT
2
2
= 2A_RMS
Decoupling the PV_IN with two 47µF X5R or X7R ceramic
capacitors is adequate for most applications.
Finally, it is possible to define the soft-start up time choos-
ing the proper value for the capacitor and the resistor
connected to TRACK/SS1 pin. If one sets minimum T_SS
= 5ms and a resistor of 4.7M, the following equation can
be solved with the maximum SV_IN = 5.5V:
C_SS
=
4.7M
• In
5ms
5.5V
= 9.2nF
5.5V – 0.6V
The standard value of 10nF and 4.7M guarantees the
minimum soft-start time of 5ms. In Figure 3, V_DDQ shows
the schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3618:
1. A ground plane is recommended. If a ground plane
layer is not used, the signal and power grounds should
be segregated with all small signal components returning
to the SGND pin at one point which is then connected to
the PGND node at the exposed pad close to the LTC3618.
2. Connect the (+) terminal of the input capacitors, C_IN,
as close as possible to the PV_INx pins, and the (–) ter-
minal as close as possible to the exposed pad PGND.
This capacitor provides the AC current into the internal
power MOSFETs.
3. Keep the switching nodes, SWx, away from all sensitive
small signal nodes FBx, ITHx, RT.
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. Connect the copper areas to PGND
(exposed pad) for best performance.
5. Connect the V_FBx pins directly to the feedback resis-
tors. The resistor divider must be connected between
V_OUTx and SGND.
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